[coreboot-gerrit] Patch merged into coreboot/master: 749559b tegra124: fix and fine tune the warm boot code
gerrit at coreboot.org
gerrit at coreboot.org
Fri Jan 9 16:50:25 CET 2015
the following patch was just integrated into master:
commit 749559b1fbee31395c93fa25f9db708d414d3a79
Author: Joseph Lo <josephl at nvidia.com>
Date: Fri Jun 27 11:22:41 2014 +0800
tegra124: fix and fine tune the warm boot code
We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same
as PLLP. But that is incorrect, BootROM had switched it to pllp_out2
with the rate 204MHz. So actually the warm boot procedure was running at
the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz.
And the CPU complex power on sequences were different with what we used
in kernel and Coreboot. Fix up the sequence as below.
* enable CPU clk
* power on CPU complex
* remove I/O clamps
* remove CPU reset
Update the time of the CPU complex power on function for record.
* power_on_partition(PARTID_CRAIL): 528 uSec
* power_on_partition(PARTID_CONC): 0 uSec
* power_on_partition(PARTID_CE0): 4 uSec
Finally, removing the redundant routine of a flow controller event with
(20 | MSEC_EVENT | MODE_STOP).
BUG=chrome-os-partner:29394
BRANCH=none
TEST=manually test LP0 with lid switch quickly and make sure the last
write to restore register successfully
Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8
Original-Signed-off-by: Joseph Lo <josephl at nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205901
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang at nvidia.com>
Original-Commit-Queue: Jimmy Zhang <jimmzhang at nvidia.com>
(cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: If21d17dc888b2c289970163e4f695423173ca03d
Reviewed-on: http://review.coreboot.org/8151
Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/8151 for details.
-gerrit
More information about the coreboot-gerrit
mailing list