[coreboot-gerrit] Patch set updated for coreboot: c79b69b intel: Use defined ACPI S3 magic values

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Fri Jan 9 09:11:19 CET 2015


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8170

-gerrit

commit c79b69ba7933bf86c8eecd9eff78f4d1209e63e5
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jan 8 20:03:18 2015 +0200

    intel: Use defined ACPI S3 magic values
    
    Unify this, until converted to CBMEM romstage_handoff.
    
    Change-Id: I2fdf44b2f654242369a9d0983a2dfa9aad1669e2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/lenovo/x201/romstage.c            | 4 ++--
 src/mainboard/packardbell/ms2290/romstage.c     | 4 ++--
 src/northbridge/intel/nehalem/northbridge.c     | 4 ++--
 src/northbridge/intel/sandybridge/early_init.c  | 4 ++--
 src/northbridge/intel/sandybridge/northbridge.c | 4 ++--
 src/northbridge/intel/sandybridge/sandybridge.h | 3 +++
 6 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 64011b1..b102993 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -305,9 +305,9 @@ void main(unsigned long bist)
 			       HIGH_MEMORY_SAVE);
 
 		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	} else {
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
 		quick_ram_check();
 	}
 #endif
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index a366d38..7ba02b4 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -289,9 +289,9 @@ void main(unsigned long bist)
 			       HIGH_MEMORY_SAVE);
 
 		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	} else {
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
 		quick_ram_check();
 	}
 #endif
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 11d335a..2c4b1ff 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -287,11 +287,11 @@ static void northbridge_enable(device_t dev)
 {
 #if CONFIG_HAVE_ACPI_RESUME
 	switch (pci_read_config32(dev, SKPAD)) {
-	case 0xcafebabe:
+	case SKPAD_NORMAL_BOOT_MAGIC:
 		printk(BIOS_DEBUG, "Normal boot.\n");
 		acpi_slp_type = 0;
 		break;
-	case 0xcafed00d:
+	case SKPAD_ACPI_S3_MAGIC:
 		printk(BIOS_DEBUG, "S3 Resume.\n");
 		acpi_slp_type = 3;
 		break;
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 3156f86..597d886 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -196,9 +196,9 @@ void northbridge_romstage_finalize(int s3resume)
 			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
 		}
 		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 	} else {
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
 	}
 #endif
 }
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 55395ea..7159700 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -416,11 +416,11 @@ static void northbridge_enable(device_t dev)
 {
 #if CONFIG_HAVE_ACPI_RESUME
 	switch (pci_read_config32(dev, SKPAD)) {
-	case 0xcafebabe:
+	case SKPAD_NORMAL_BOOT_MAGIC:
 		printk(BIOS_DEBUG, "Normal boot.\n");
 		acpi_slp_type=0;
 		break;
-	case 0xcafed00d:
+	case SKPAD_ACPI_S3_MAGIC:
 		printk(BIOS_DEBUG, "S3 Resume.\n");
 		acpi_slp_type=3;
 		break;
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 0790ae8..ea760a9 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -99,6 +99,9 @@
 
 #define SKPAD		0xdc	/* Scratchpad Data */
 
+#define SKPAD_ACPI_S3_MAGIC	0xcafed00d
+#define SKPAD_NORMAL_BOOT_MAGIC	0xcafebabe
+
 /* Device 0:1.0 PCI configuration space (PCI Express) */
 
 #define BCTRL1		0x3e	/* 16bit */



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