[coreboot-gerrit] Patch set updated for coreboot: 05d7d40 arm: Change MMIO function parameter order to match x86
Kevin Paul Herbert (kph@meraki.net)
gerrit at coreboot.org
Wed Jan 7 21:55:24 CET 2015
Kevin Paul Herbert (kph at meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7924
-gerrit
commit 05d7d40e09000ea6692d85caa92ff502f9842cf2
Author: Kevin Paul Herbert <kph at meraki.net>
Date: Wed Dec 24 20:49:42 2014 -0800
arm: Change MMIO function parameter order to match x86
x86 defines the I/O accessors write8/write16/write32 as
writeN(addr, val) while ARM defined them as writeN(val, addr).
Change ARM to be the same as x86.
Change-Id: I26606e7487405fe1d6bb495573a3a7c0967acf64
Signed-off-by: Kevin Paul Herbert <kph at meraki.net>
---
src/arch/arm/include/arch/io.h | 4 +-
src/arch/arm/include/armv4/arch/arch_io.h | 6 +-
src/arch/arm/include/armv7/arch/arch_io.h | 6 +-
src/cpu/allwinner/a10/clock.c | 12 +--
src/cpu/allwinner/a10/gpio.c | 2 +-
src/cpu/allwinner/a10/pinmux.c | 4 +-
src/cpu/allwinner/a10/raminit.c | 28 +++----
src/cpu/allwinner/a10/timer.c | 6 +-
src/cpu/allwinner/a10/twi.c | 14 ++--
src/cpu/allwinner/a10/uart.c | 12 +--
src/cpu/ti/am335x/uart.c | 52 ++++++------
src/mainboard/cubietech/cubieboard/bootblock.c | 14 ++--
src/soc/nvidia/tegra/apbmisc.c | 4 +-
src/soc/nvidia/tegra/gpio.c | 4 +-
src/soc/nvidia/tegra/i2c.c | 6 +-
src/soc/nvidia/tegra/pingroup.c | 2 +-
src/soc/nvidia/tegra/pinmux.c | 2 +-
src/soc/nvidia/tegra/usb.c | 64 ++++-----------
src/soc/nvidia/tegra124/clock.c | 105 +++++++++----------------
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 92 +++++++++++-----------
src/soc/nvidia/tegra124/power.c | 6 +-
src/soc/nvidia/tegra124/spi.c | 23 +++---
src/soc/nvidia/tegra124/uart.c | 19 +++--
src/soc/samsung/exynos5420/dmc_init_ddr3.c | 4 +-
src/soc/samsung/exynos5420/dp_lowlevel.c | 2 +-
src/soc/samsung/exynos5420/i2c.c | 12 +--
26 files changed, 217 insertions(+), 288 deletions(-)
diff --git a/src/arch/arm/include/arch/io.h b/src/arch/arm/include/arch/io.h
index e537297..0320264 100644
--- a/src/arch/arm/include/arch/io.h
+++ b/src/arch/arm/include/arch/io.h
@@ -32,9 +32,9 @@
* re-factor all code to specify the data length intended.
*/
#define readb(a) read8(a)
-#define writeb(v,a) write8(v,a)
+#define writeb(v,a) write8(a,v)
#define readl(a) read32(a)
-#define writel(v,a) write32(v,a)
+#define writel(v,a) write32(a,v)
/*
* Clear and set bits in one shot. These macros can be used to clear and
diff --git a/src/arch/arm/include/armv4/arch/arch_io.h b/src/arch/arm/include/armv4/arch/arch_io.h
index 72653da..cf5a9e1 100644
--- a/src/arch/arm/include/armv4/arch/arch_io.h
+++ b/src/arch/arm/include/armv4/arch/arch_io.h
@@ -40,17 +40,17 @@ static inline uint32_t read32(const void *addr)
return *(volatile uint32_t *)addr;
}
-static inline void write8(uint8_t val, void *addr)
+static inline void write8(void *addr, uint8_t val)
{
*(volatile uint8_t *)addr = val;
}
-static inline void write16(uint16_t val, void *addr)
+static inline void write16(void *addr, uint16_t val)
{
*(volatile uint16_t *)addr = val;
}
-static inline void write32(uint32_t val, void *addr)
+static inline void write32(void *addr, uint32_t val)
{
*(volatile uint32_t *)addr = val;
}
diff --git a/src/arch/arm/include/armv7/arch/arch_io.h b/src/arch/arm/include/armv7/arch/arch_io.h
index 360fa64..53eafc6 100644
--- a/src/arch/arm/include/armv7/arch/arch_io.h
+++ b/src/arch/arm/include/armv7/arch/arch_io.h
@@ -44,21 +44,21 @@ static inline uint32_t read32(const void *addr)
return *(volatile uint32_t *)addr;
}
-static inline void write8(uint8_t val, void *addr)
+static inline void write8(void *addr, uint8_t val)
{
dmb();
*(volatile uint8_t *)addr = val;
dmb();
}
-static inline void write16(uint16_t val, void *addr)
+static inline void write16(void *addr, uint16_t val)
{
dmb();
*(volatile uint16_t *)addr = val;
dmb();
}
-static inline void write32(uint32_t val, void *addr)
+static inline void write32(void *addr, uint32_t val)
{
dmb();
*(volatile uint32_t *)addr = val;
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index f189aea..c73566a 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -28,7 +28,7 @@ void a1x_periph_clock_enable(enum a1x_clken periph)
addr = (void *)A1X_CCM_BASE + (periph >> 5);
reg32 = read32(addr);
reg32 |= 1 << (periph & 0x1f);
- write32(reg32, addr);
+ write32(addr, reg32);
}
/**
@@ -44,7 +44,7 @@ void a1x_periph_clock_disable(enum a1x_clken periph)
addr = (void *)A1X_CCM_BASE + (periph >> 5);
reg32 = read32(addr);
reg32 &= ~(1 << (periph & 0x1f));
- write32(reg32, addr);
+ write32(addr, reg32);
}
/**
@@ -88,7 +88,7 @@ void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p)
reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) |
PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p));
reg32 |= PLL5_PLL_ENABLE;
- write32(reg32, &ccm->pll5_cfg);
+ write32(&ccm->pll5_cfg, reg32);
}
/**
@@ -166,7 +166,7 @@ static void cpu_clk_src_switch(u32 clksel_bits)
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= clksel_bits & CPU_CLK_SRC_MASK;
- write32(reg32, &ccm->cpu_ahb_apb0_cfg);
+ write32(&ccm->cpu_ahb_apb0_cfg, reg32);
}
static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
@@ -179,7 +179,7 @@ static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK;
reg32 |= (ahb_exp << 4) & AHB_DIV_MASK;
reg32 |= (apb0_exp << 8) & APB0_DIV_MASK;
- write32(reg32, &ccm->cpu_ahb_apb0_cfg);
+ write32(&ccm->cpu_ahb_apb0_cfg, reg32);
}
static void spin_delay(u32 loops)
@@ -262,7 +262,7 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
change_sys_divisors(axi, ahb_exp, apb0_exp);
/* Configure PLL1 at the desired frequency */
- write32(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
+ write32(&ccm->pll1_cfg, pll1_table[i].pll1_cfg);
spin_delay(8);
cpu_clk_src_switch(CPU_CLK_SRC_PLL1);
diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c
index 5fca2d7..95854e5 100644
--- a/src/cpu/allwinner/a10/gpio.c
+++ b/src/cpu/allwinner/a10/gpio.c
@@ -76,7 +76,7 @@ void gpio_write(u8 port, u32 val)
if ((port > GPS))
return;
- write32(val, &gpio->port[port].dat);
+ write32(&gpio->port[port].dat, val);
}
/**
diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c
index de87440..f5ed19a 100644
--- a/src/cpu/allwinner/a10/pinmux.c
+++ b/src/cpu/allwinner/a10/pinmux.c
@@ -33,7 +33,7 @@ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func)
reg32 = read32(&gpio->port[port].cfg[reg]);
reg32 &= ~(0xf << bit);
reg32 |= (pad_func & 0xf) << bit;
- write32(reg32, &gpio->port[port].cfg[reg]);
+ write32(&gpio->port[port].cfg[reg], reg32);
}
/**
@@ -74,6 +74,6 @@ void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func)
reg32 &= ~(0xf << bit);
reg32 |= (pad_func & 0xf) << bit;
}
- write32(reg32, &gpio->port[port].cfg[reg]);
+ write32(&gpio->port[port].cfg[reg], reg32);
}
}
diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c
index de24e03..28fd408 100644
--- a/src/cpu/allwinner/a10/raminit.c
+++ b/src/cpu/allwinner/a10/raminit.c
@@ -118,7 +118,7 @@ static void mctl_configure_hostport(void)
u32 i;
for (i = 0; i < 32; i++)
- write32(hpcr_value[i], &dram->hpcr[i]);
+ write32(&dram->hpcr[i], hpcr_value[i]);
}
static void mctl_setup_dram_clock(u32 clk)
@@ -333,9 +333,9 @@ static void dramc_set_autorefresh_cycle(u32 clk)
tmp_val = tmp_val * 9 - 200;
reg32 |= tmp_val << 8;
reg32 |= 0x8 << 24;
- write32(reg32, &dram->drr);
+ write32(&dram->drr, reg32);
} else {
- write32(0x0, &dram->drr);
+ write32(&dram->drr, 0x0);
}
}
@@ -360,7 +360,7 @@ unsigned long dramc_init(struct dram_para *para)
a1x_gate_dram_clock_output();
/* select dram controller 1 */
- write32(DRAM_CSEL_MAGIC, &dram->csel);
+ write32(&dram->csel, DRAM_CSEL_MAGIC);
mctl_itm_disable();
mctl_enable_dll0(para->tpr3);
@@ -390,7 +390,7 @@ unsigned long dramc_init(struct dram_para *para)
reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
reg32 |= DRAM_DCR_CMD_RANK_ALL;
reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
- write32(reg32, &dram->dcr);
+ write32(&dram->dcr, reg32);
/* dram clock on */
a1x_ungate_dram_clock_output();
@@ -405,21 +405,21 @@ unsigned long dramc_init(struct dram_para *para)
reg32 = ((para->zq) >> 8) & 0xfffff;
reg32 |= ((para->zq) & 0xff) << 20;
reg32 |= (para->zq) & 0xf0000000;
- write32(reg32, &dram->zqcr0);
+ write32(&dram->zqcr0, reg32);
/* set I/O configure register */
reg32 = 0x00cc0000;
reg32 |= (para->odt_en) & 0x3;
reg32 |= ((para->odt_en) & 0x3) << 30;
- write32(reg32, &dram->iocr);
+ write32(&dram->iocr, reg32);
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock);
/* set timing parameters */
- write32(para->tpr0, &dram->tpr0);
- write32(para->tpr1, &dram->tpr1);
- write32(para->tpr2, &dram->tpr2);
+ write32(&dram->tpr0, para->tpr0);
+ write32(&dram->tpr1, para->tpr1);
+ write32(&dram->tpr2, para->tpr2);
if (para->type == DRAM_MEMORY_TYPE_DDR3) {
reg32 = DRAM_MR_BURST_LENGTH(0x0);
@@ -430,11 +430,11 @@ unsigned long dramc_init(struct dram_para *para)
reg32 |= DRAM_MR_CAS_LAT(para->cas);
reg32 |= DRAM_MR_WRITE_RECOVERY(0x5);
}
- write32(reg32, &dram->mr);
+ write32(&dram->mr, reg32);
- write32(para->emr1, &dram->emr);
- write32(para->emr2, &dram->emr2);
- write32(para->emr3, &dram->emr3);
+ write32(&dram->emr, para->emr1);
+ write32(&dram->emr2, para->emr2);
+ write32(&dram->emr3, para->emr3);
/* set DQS window mode */
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c
index 7d5d141..5082114 100644
--- a/src/cpu/allwinner/a10/timer.c
+++ b/src/cpu/allwinner/a10/timer.c
@@ -24,13 +24,13 @@ void init_timer(void)
{
u32 reg32;
/* Load the timer rollover value */
- write32(0xffffffff, &tmr0->interval);
+ write32(&tmr0->interval, 0xffffffff);
/* Configure the timer to run from 24MHz oscillator, no prescaler */
reg32 = TIMER_CTRL_PRESC_DIV_EXP(0);
reg32 |= TIMER_CTRL_CLK_SRC_OSC24M;
reg32 |= TIMER_CTRL_RELOAD;
reg32 |= TIMER_CTRL_TMR_EN;
- write32(reg32, &tmr0->ctrl);
+ write32(&tmr0->ctrl, reg32);
}
void udelay(unsigned usec)
@@ -61,6 +61,6 @@ void udelay(unsigned usec)
*/
u8 a1x_get_cpu_chip_revision(void)
{
- write32(0, &timer_module->cpu_cfg);
+ write32(&timer_module->cpu_cfg, 0);
return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
}
diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c
index d6a0127..2e516c6 100644
--- a/src/cpu/allwinner/a10/twi.c
+++ b/src/cpu/allwinner/a10/twi.c
@@ -42,7 +42,7 @@ static void configure_clock(struct a1x_twi *twi, u32 speed_hz)
/* Pre-divide the clock by 8 */
n = 3;
m = (apb_clk >> n) / speed_hz;
- write32(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
+ write32(&twi->clk, TWI_CLK_M(m) | TWI_CLK_N(n));
}
void a1x_twi_init(u8 bus, u32 speed_hz)
@@ -53,9 +53,9 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
configure_clock(twi, speed_hz);
/* Enable the I²C bus */
- write32(TWI_CTL_BUS_EN, &twi->ctl);
+ write32(&twi->ctl, TWI_CTL_BUS_EN);
/* Issue soft reset */
- write32(1, &twi->reset);
+ write32(&twi->reset, 1);
while (i-- && read32(&twi->reset))
udelay(1);
@@ -63,12 +63,12 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
static void clear_interrupt_flag(struct a1x_twi *twi)
{
- write32(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
+ write32(&twi->ctl, read32(&twi->ctl) & ~TWI_CTL_INT_FLAG);
}
static void i2c_send_data(struct a1x_twi *twi, u8 data)
{
- write32(data, &twi->data);
+ write32(&twi->data, data);
clear_interrupt_flag(twi);
}
@@ -90,7 +90,7 @@ static void i2c_send_start(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_START;
- write32(reg32, &twi->ctl);
+ write32(&twi->ctl, reg32);
/* M_START is automatically cleared after condition is transmitted */
i = TWI_TIMEOUT;
@@ -106,7 +106,7 @@ static void i2c_send_stop(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_STOP;
- write32(reg32, &twi->ctl);
+ write32(&twi->ctl, reg32);
}
static int i2c_read(unsigned bus, unsigned chip, unsigned addr,
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
index 407bd86..3c02867 100644
--- a/src/cpu/allwinner/a10/uart.c
+++ b/src/cpu/allwinner/a10/uart.c
@@ -22,10 +22,10 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
div = (u16) uart_baudrate_divisor(baud_rate,
uart_platform_refclk(), 16);
/* Enable access to Divisor Latch register */
- write32(UART8250_LCR_DLAB, &uart->lcr);
+ write32(&uart->lcr, UART8250_LCR_DLAB);
/* Set baudrate */
- write32((div >> 8) & 0xff, &uart->dlh);
- write32(div & 0xff, &uart->dll);
+ write32(&uart->dlh, (div >> 8) & 0xff);
+ write32(&uart->dll, div & 0xff);
/* Set line control */
reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK;
switch (parity) {
@@ -40,12 +40,12 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
default:
break;
}
- write32(reg32, &uart->lcr);
+ write32(&uart->lcr, reg32);
}
static void a10_uart_enable_fifos(struct a10_uart *uart)
{
- write32(UART8250_FCR_FIFO_EN, &uart->fcr);
+ write32(&uart->fcr, UART8250_FCR_FIFO_EN);
}
static int tx_fifo_full(struct a10_uart *uart)
@@ -83,7 +83,7 @@ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data)
{
while (tx_fifo_full(uart)) ;
- return write32(data, &uart->thr);
+ return write32(&uart->thr, data);
}
diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c
index 5756834..4518ff8 100644
--- a/src/cpu/ti/am335x/uart.c
+++ b/src/cpu/ti/am335x/uart.c
@@ -42,88 +42,88 @@ static void am335x_uart_init(struct am335x_uart *uart, uint16_t div)
uint16_t lcr_orig, efr_orig, mcr_orig;
/* reset the UART */
- write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc);
+ write16(&uart->sysc, uart->sysc | SYSC_SOFTRESET);
while (!(read16(&uart->syss) & SYSS_RESETDONE))
;
/* 1. switch to register config mode B */
lcr_orig = read16(&uart->lcr);
- write16(0xbf, &uart->lcr);
+ write16(&uart->lcr, 0xbf);
/*
* 2. Set EFR ENHANCED_EN bit. To access this bit, registers must
* be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1.
*/
efr_orig = read16(&uart->efr);
- write16(efr_orig | EFR_ENHANCED_EN, &uart->efr);
+ write16(&uart->efr, efr_orig | EFR_ENHANCED_EN);
/* 3. Switch to register config mode A */
- write16(0x80, &uart->lcr);
+ write16(&uart->lcr, 0x80);
/* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */
mcr_orig = read16(&uart->mcr);
- write16(mcr_orig | MCR_TCR_TLR, &uart->mcr);
+ write16(&uart->mcr, mcr_orig | MCR_TCR_TLR);
/* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */
- write16(FCR_FIFO_EN, &uart->fcr);
+ write16(&uart->fcr, FCR_FIFO_EN);
/* 6. Switch to configuration mode B */
- write16(0xbf, &uart->lcr);
+ write16(&uart->lcr, 0xbf);
/* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */
/* 9. Restore original EFR value */
- write16(efr_orig, &uart->efr);
+ write16(&uart->efr, efr_orig);
/* 10. Switch to config mode A */
- write16(0x80, &uart->lcr);
+ write16(&uart->lcr, 0x80);
/* 11. Restore original MCR value */
- write16(mcr_orig, &uart->mcr);
+ write16(&uart->mcr, mcr_orig);
/* 12. Restore original LCR value */
- write16(lcr_orig, &uart->lcr);
+ write16(&uart->lcr, lcr_orig);
/* Protocol, baud rate and interrupt settings */
/* 1. Disable UART access to DLL and DLH registers */
- write16(read16(&uart->mdr1) | 0x7, &uart->mdr1);
+ write16(&uart->mdr1, read16(&uart->mdr1) | 0x7);
/* 2. Switch to config mode B */
- write16(0xbf, &uart->lcr);
+ write16(&uart->lcr, 0xbf);
/* 3. Enable access to IER[7:4] */
- write16(efr_orig | EFR_ENHANCED_EN, &uart->efr);
+ write16(&uart->efr, efr_orig | EFR_ENHANCED_EN);
/* 4. Switch to operational mode */
- write16(0x0, &uart->lcr);
+ write16(&uart->lcr, 0x0);
/* 5. Clear IER */
- write16(0x0, &uart->ier);
+ write16(&uart->ier, 0x0);
/* 6. Switch to config mode B */
- write16(0xbf, &uart->lcr);
+ write16(&uart->lcr, 0xbf);
/* 7. Set dll and dlh to the desired values (table 19-25) */
- write16((div >> 8), &uart->dlh);
- write16((div & 0xff), &uart->dll);
+ write16(&uart->dlh, (div >> 8));
+ write16(&uart->dll, (div & 0xff));
/* 8. Switch to operational mode to access ier */
- write16(0x0, &uart->lcr);
+ write16(&uart->lcr, 0x0);
/* 9. Clear ier to disable all interrupts */
- write16(0x0, &uart->ier);
+ write16(&uart->ier, 0x0);
/* 10. Switch to config mode B */
- write16(0xbf, &uart->lcr);
+ write16(&uart->lcr, 0xbf);
/* 11. Restore efr */
- write16(efr_orig, &uart->efr);
+ write16(&uart->efr, efr_orig);
/* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */
- write16(0x3, &uart->lcr);
+ write16(&uart->lcr, 0x3);
/* 13. Load the new UART mode */
- write16(0x0, &uart->mdr1);
+ write16(&uart->mdr1, 0x0);
}
/*
@@ -145,7 +145,7 @@ static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data)
{
while (!(read16(&uart->lsr) & LSR_TXFIFOE));
- return write8(data, &uart->thr);
+ return write8(&uart->thr, data);
}
unsigned int uart_platform_refclk(void)
diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c
index 360f914..e4a0313 100644
--- a/src/mainboard/cubietech/cubieboard/bootblock.c
+++ b/src/mainboard/cubietech/cubieboard/bootblock.c
@@ -38,12 +38,12 @@ static void cubieboard_set_sys_clock(void)
struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
/* Switch CPU clock to main oscillator */
- write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg);
+ write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT);
/* Configure the PLL1. The value is the same one used by u-boot
* P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz
*/
- write32(0xa1005000, &ccm->pll1_cfg);
+ write32(&ccm->pll1_cfg, 0xa1005000);
/* FIXME: Delay to wait for PLL to lock */
u32 wait = 1000;
@@ -53,7 +53,7 @@ static void cubieboard_set_sys_clock(void)
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= CPU_CLK_SRC_PLL1;
- write32(reg32, &ccm->cpu_ahb_apb0_cfg);
+ write32(&ccm->cpu_ahb_apb0_cfg, reg32);
}
static void cubieboard_setup_clocks(void)
@@ -62,12 +62,12 @@ static void cubieboard_setup_clocks(void)
cubieboard_set_sys_clock();
/* Configure the clock source for APB1. This drives our UART */
- write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0),
- &ccm->apb1_clk_div_cfg);
+ write32(&ccm->apb1_clk_div_cfg,
+ APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0));
/* Configure the clock for SD0 */
- write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0)
- | SDx_RAT_M(1), &ccm->sd0_clk_cfg);
+ write32(&ccm->sd0_clk_cfg,
+ SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1));
/* Enable clock to SD0 */
a1x_periph_clock_enable(A1X_CLKEN_MMC0);
diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c
index 5983d54..9034c97 100644
--- a/src/soc/nvidia/tegra/apbmisc.c
+++ b/src/soc/nvidia/tegra/apbmisc.c
@@ -26,10 +26,10 @@ static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;
void enable_jtag(void)
{
- write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
+ write32(&misc->pp_config_ctl, PP_CONFIG_CTL_JTAG);
}
void clamp_tristate_inputs(void)
{
- write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
+ write32(&misc->pp_pinmux_global, PP_PINMUX_CLAMP_INPUTS);
}
diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c
index b10cded..833020d 100644
--- a/src/soc/nvidia/tegra/gpio.c
+++ b/src/soc/nvidia/tegra/gpio.c
@@ -98,8 +98,8 @@ static void gpio_write_port(int index, size_t offset, u32 mask, u32 value)
u32 new_reg = (reg & ~mask) | (value & mask);
if (new_reg != reg) {
- write32(new_reg, (u8 *)&gpio_banks[bank] + offset +
- port * sizeof(u32));
+ write32((u8 *)&gpio_banks[bank] + offset + port * sizeof(u32),
+ new_reg);
}
}
diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index 26c2559..a68129a 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read,
rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT;
while (header_words && tx_empty) {
- write32(*headers++, ®s->tx_packet_fifo);
+ write32(®s->tx_packet_fifo, *headers++);
header_words--;
tx_empty--;
}
@@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read,
int todo = MIN(data_len, sizeof(word));
memcpy(&word, data, todo);
- write32(word, ®s->tx_packet_fifo);
+ write32(®s->tx_packet_fifo, word);
data_len -= todo;
data += sizeof(word);
tx_empty--;
@@ -203,5 +203,5 @@ void i2c_init(unsigned bus)
{
struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base;
- write32(I2C_CNFG_PACKET_MODE_EN, ®s->cnfg);
+ write32(®s->cnfg, I2C_CNFG_PACKET_MODE_EN);
}
diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c
index 858cb44..332e05a 100644
--- a/src/soc/nvidia/tegra/pingroup.c
+++ b/src/soc/nvidia/tegra/pingroup.c
@@ -26,7 +26,7 @@ static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE;
void pingroup_set_config(int group_index, uint32_t config)
{
- write32(config, &pingroup_regs[group_index]);
+ write32(&pingroup_regs[group_index], config);
}
uint32_t pingroup_get_config(int group_index)
diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c
index 6e4b3ff..f28b026 100644
--- a/src/soc/nvidia/tegra/pinmux.c
+++ b/src/soc/nvidia/tegra/pinmux.c
@@ -26,7 +26,7 @@ static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE;
void pinmux_set_config(int pin_index, uint32_t config)
{
- write32(config, &pinmux_regs[pin_index]);
+ write32(&pinmux_regs[pin_index], config);
}
uint32_t pinmux_get_config(int pin_index)
diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c
index e0455ed..9bd639e 100644
--- a/src/soc/nvidia/tegra/usb.c
+++ b/src/soc/nvidia/tegra/usb.c
@@ -35,61 +35,27 @@ void usb_setup_utmip(struct usb_ctlr *usb)
udelay(1);
/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
- write32(0x8 << 25 | /* HS slew rate [10:4] */
- 0x3 << 22 | /* HS driver output 'SETUP' [6:4] */
- 0 << 21 | /* LS bias selection */
- 0 << 18 | /* PDZI pwrdn */
- 0 << 16 | /* PD2 pwrdn */
- 0 << 14 | /* PD pwrdn */
- 1 << 13 | /* (rst) HS receiver terminations */
- 0x1 << 10 | /* (rst) LS falling slew rate */
- 0x1 << 8 | /* (rst) LS rising slew rate */
- 0x4 << 0 | /* HS driver output 'SETUP' [3:0] */
- 0, &usb->utmip.xcvr0);
- write32(0x7 << 18 | /* Termination range adjustment */
- 0 << 4 | /* PDDR pwrdn */
- 0 << 2 | /* PDCHRP pwrdn */
- 0 << 0 | /* PDDISC pwrdn */
- 0, &usb->utmip.xcvr1);
- write32(1 << 19 | /* FS send initial J before sync(?) */
- 1 << 16 | /* (rst) Allow stuff error on SoP */
- 1 << 9 | /* (rst) Check disc only on EoP */
- 0, &usb->utmip.tx);
- write32(0x2 << 30 | /* (rst) Keep pattern on active */
- 1 << 28 | /* (rst) Realign inertia on pkt */
- 0x1 << 24 | /* (rst) edges-1 to move sampling */
- 0x3 << 21 | /* (rst) squelch delay on EoP */
- 0x11 << 15 | /* cycles until IDLE */
- 0x10 << 10 | /* elastic input depth */
- 0, &usb->utmip.hsrx0);
+ write32(&usb->utmip.xcvr0,
+ 0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0);
+ write32(&usb->utmip.xcvr1, 0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0);
+ write32(&usb->utmip.tx, 1 << 19 | 1 << 16 | 1 << 9 | 0);
+ write32(&usb->utmip.hsrx0,
+ 0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0);
/* U-Boot claims the USBD values for these are used across all UTMI+
* PHYs. That sounds so horribly wrong that I'm not going to implement
* it, but keep it in mind if we're ever not using the USBD port. */
- write32(0x1 << 24 | /* HS disconnect detect level [2] */
- 1 << 23 | /* (rst) IDPD value */
- 1 << 22 | /* (rst) IDPD select */
- 1 << 11 | /* (rst) OTG pwrdn */
- 0 << 10 | /* bias pwrdn */
- 0x1 << 2 | /* HS disconnect detect level [1:0] */
- 0x2 << 0 | /* HS squelch detect level */
- 0, &usb->utmip.bias0);
+ write32(&usb->utmip.bias0,
+ 0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0);
- write32(khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */
- 1 << 2 | /* (rst) VBUS wakeup pwrdn */
- 0 << 0 | /* PDTRK pwrdn */
- 0, &usb->utmip.bias1);
+ write32(&usb->utmip.bias1, khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0);
- write32(0xffff << 16 | /* (rst) */
- 25 * khz / 10 << 0 | /* TODO: what's this, really? */
- 0, &usb->utmip.debounce);
+ write32(&usb->utmip.debounce, 0xffff << 16 | 25 * khz / 10 << 0 | 0);
udelay(1);
setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
- write32(1 << 12 | /* UTMI+ enable */
- 0 << 11 | /* UTMI+ reset */
- 0, &usb->suspend_ctrl);
+ write32(&usb->suspend_ctrl, 1 << 12 | 0 << 11 | 0);
}
/*
@@ -105,7 +71,7 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
{
int timeout = 1000;
- write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */
+ write32(&usb->ehci_usbcmd, 1 << 1); /* Host Controller Reset */
/* TODO: Resets are long, find way to parallelize... or just use XHCI */
while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
/* wait for HC to reset */;
@@ -115,7 +81,7 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
return;
}
- write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */
- write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */
- write32(0x10 << 16, &usb->tx_fill_tuning); /* Tx FIFO Burst thresh */
+ write32(&usb->usb_mode, 3 << 0); /* Controller mode: HOST */
+ write32(&usb->lpm_ctrl, type << 29); /* Parallel transceiver selct */
+ write32(&usb->tx_fill_tuning, 0x10 << 16); /* Tx FIFO Burst thresh */
}
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index af2f96a..48bf765 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -184,11 +184,11 @@ void clock_init_arm_generic_timer(void)
__asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq));
// Record the system timer frequency.
- write32(freq, &sysctr->cntfid0);
+ write32(&sysctr->cntfid0, freq);
// Enable the system counter.
uint32_t cntcr = read32(&sysctr->cntcr);
cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
- write32(cntcr, &sysctr->cntcr);
+ write32(&sysctr->cntcr, cntcr);
}
#define SOR0_CLK_SEL0 (1 << 14)
@@ -241,25 +241,14 @@ static void init_utmip_pll(void)
clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
udelay(1);
- write32(80 << 16 | /* (rst) phy_divn */
- 1 << 8 | /* (rst) phy_divm */
- 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */
+ write32(&clk_rst->utmip_pll_cfg0, 80 << 16 | 1 << 8 | 0); /* 960MHz * 1 / 80 == 12 MHz */
- write32(CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
- 0 << 16 | /* PLLU pwrdn */
- 0 << 14 | /* pll_enable pwrdn */
- 0 << 12 | /* pll_active pwrdn */
- CEIL_DIV(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */
- 0, &clk_rst->utmip_pll_cfg1);
+ write32(&clk_rst->utmip_pll_cfg1,
+ CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0);
/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
- write32(0 << 24 | /* SAMP_D/XDEV pwrdn */
- CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
- CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
- 0 << 4 | /* SAMP_C/USB3 pwrdn */
- 0 << 2 | /* SAMP_B/XHOST pwrdn */
- 0 << 0 | /* SAMP_A/USBD pwrdn */
- 0, &clk_rst->utmip_pll_cfg2);
+ write32(&clk_rst->utmip_pll_cfg2,
+ 0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0);
setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
}
@@ -396,8 +385,8 @@ clock_display(u32 frequency)
* been determined through trial and error (must lead to div 13 at 24MHz). */
void clock_early_uart(void)
{
- write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE |
- CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta);
+ write32(&clk_rst->clk_src_uarta,
+ CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900));
setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA);
udelay(2);
clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA);
@@ -484,28 +473,24 @@ void clock_cpu0_config_and_reset(void *entry)
{
void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
- write32(CONFIG_STACK_TOP, &maincpu_stack_pointer);
- write32((uintptr_t)entry, &maincpu_entry_point);
- write32((uintptr_t)&maincpu_setup, evp_cpu_reset);
+ write32(&maincpu_stack_pointer, CONFIG_STACK_TOP);
+ write32(&maincpu_entry_point, (uintptr_t)entry);
+ write32(evp_cpu_reset, (uintptr_t)&maincpu_setup);
/* Set active CPU cluster to G */
clrbits_le32(&flow->cluster_control, 1);
// Set up cclk_brst and divider.
- write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) |
- (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) |
- (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) |
- (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) |
- (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28),
- &clk_rst->cclk_brst_pol);
- write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB,
- &clk_rst->super_cclk_div);
+ write32(&clk_rst->cclk_brst_pol,
+ (CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28));
+ write32(&clk_rst->super_cclk_div,
+ CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB);
// Enable the clocks for CPUs 0-3.
uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr);
cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP |
CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP;
- write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr);
+ write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr);
// Enable other CPU related clocks.
setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
@@ -513,36 +498,23 @@ void clock_cpu0_config_and_reset(void *entry)
setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP);
// Disable the reset on the non-CPU parts of the fast cluster.
- write32(CRC_RST_CPUG_CLR_NONCPU,
- &clk_rst->rst_cpug_cmplx_clr);
+ write32(&clk_rst->rst_cpug_cmplx_clr, CRC_RST_CPUG_CLR_NONCPU);
// Disable the various resets on the CPUs.
- write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 |
- CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 |
- CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 |
- CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 |
- CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 |
- CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 |
- CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 |
- CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 |
- CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
- &clk_rst->rst_cpug_cmplx_clr);
+ write32(&clk_rst->rst_cpug_cmplx_clr,
+ CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG);
// Disable the reset on the non-CPU parts of the slow cluster.
- write32(CRC_RST_CPULP_CLR_NONCPU,
- &clk_rst->rst_cpulp_cmplx_clr);
+ write32(&clk_rst->rst_cpulp_cmplx_clr, CRC_RST_CPULP_CLR_NONCPU);
// Disable the various resets on the LP CPU.
- write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 |
- CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 |
- CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
- &clk_rst->rst_cpulp_cmplx_clr);
+ write32(&clk_rst->rst_cpulp_cmplx_clr,
+ CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG);
}
void clock_halt_avp(void)
{
for (;;) {
- write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
- FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
- &flow->halt_cop_events);
+ write32(&flow->halt_cop_events,
+ FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT);
}
}
@@ -559,13 +531,12 @@ void clock_init(void)
/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
* features section in the TRM). */
- write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
- &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */
- write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out);
- write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
- SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
- &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */
+ write32(&clk_rst->clk_sys_rate,
+ 1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT); /* pclk = hclk = sclk/2 */
+ write32(&clk_rst->pllc_out,
+ CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN);
+ write32(&clk_rst->sclk_brst_pol,
+ SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */
/* Change the oscillator drive strength (from U-Boot -- why?) */
clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK,
@@ -583,16 +554,10 @@ void clock_init(void)
clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
- write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
- (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
- &clk_rst->pllp_outa);
- write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
- (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
- &clk_rst->pllp_outb);
+ write32(&clk_rst->pllp_outa,
+ (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT);
+ write32(&clk_rst->pllp_outb,
+ (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT);
/* init pllx */
init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc,
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index 0b519d6..6b22b80 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -274,17 +274,17 @@ inline static void write32(uint32_t val, void *addr)
inline static void setbits32(uint32_t bits, void *addr)
{
- write32(read32(addr) | bits, addr);
+ write32(addr, read32(addr) | bits);
}
inline static void clrbits32(uint32_t bits, void *addr)
{
- write32(read32(addr) & ~bits, addr);
+ write32(addr, read32(addr) & ~bits);
}
static void __attribute__((noreturn)) reset(void)
{
- write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
+ write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST);
halt();
}
@@ -329,7 +329,7 @@ static void config_oscillator(void)
osc_ctrl &= ~OSC_XOFS_MASK;
osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
osc_ctrl |= OSC_XOE;
- write32(osc_ctrl, clk_rst_osc_ctrl_ptr);
+ write32(clk_rst_osc_ctrl_ptr, osc_ctrl);
}
static void config_pllu(void)
@@ -374,17 +374,17 @@ static void config_pllu(void)
// Configure PLLU.
uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
- write32(base, clk_rst_pllu_base_ptr);
+ write32(clk_rst_pllu_base_ptr, base);
uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
(lfcon << PLLU_LFCON_SHIFT);
- write32(misc, clk_rst_pllu_misc_ptr);
+ write32(clk_rst_pllu_misc_ptr, misc);
// Enable PLLU.
base &= ~PLLU_BYPASS;
base |= PLLU_ENABLE;
- write32(base, clk_rst_pllu_base_ptr);
+ write32(clk_rst_pllu_base_ptr, base);
misc |= PLLU_LOCK_ENABLE;
- write32(misc, clk_rst_pllu_misc_ptr);
+ write32(clk_rst_pllu_misc_ptr, misc);
}
static void config_tsc(void)
@@ -392,26 +392,26 @@ static void config_tsc(void)
// Tell the TSC the oscillator frequency.
switch (get_osc_freq()) {
case OSC_FREQ_12:
- write32(12000000, sysctr_cntfid0_ptr);
+ write32(sysctr_cntfid0_ptr, 12000000);
break;
case OSC_FREQ_48:
- write32(48000000, sysctr_cntfid0_ptr);
+ write32(sysctr_cntfid0_ptr, 48000000);
break;
case OSC_FREQ_16P8:
- write32(16800000, sysctr_cntfid0_ptr);
+ write32(sysctr_cntfid0_ptr, 16800000);
break;
case OSC_FREQ_19P2:
- write32(19200000, sysctr_cntfid0_ptr);
+ write32(sysctr_cntfid0_ptr, 19200000);
break;
case OSC_FREQ_38P4:
- write32(38400000, sysctr_cntfid0_ptr);
+ write32(sysctr_cntfid0_ptr, 38400000);
break;
case OSC_FREQ_26:
- write32(26000000, sysctr_cntfid0_ptr);
+ write32(sysctr_cntfid0_ptr, 26000000);
break;
default:
// Default to 13MHz.
- write32(13000000, sysctr_cntfid0_ptr);
+ write32(sysctr_cntfid0_ptr, 13000000);
break;
}
@@ -426,7 +426,7 @@ static void config_tsc(void)
static void config_core_sight(void)
{
// Enable the CoreSight clock.
- write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
+ write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE);
/*
* De-assert CoreSight reset.
@@ -434,22 +434,22 @@ static void config_core_sight(void)
* now. It will be restored to its original clock source
* when the CPU-side restoration code runs.
*/
- write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
+ write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST);
}
static void config_mselect(void)
{
// Set MSELECT clock source to PLLP with 1:4 divider.
- write32((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0,
- clk_rst_clk_src_mselect_ptr);
+ write32(clk_rst_clk_src_mselect_ptr,
+ (6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0);
// Enable clock to MSELECT.
- write32(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr);
+ write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_MSELECT);
udelay(2);
// Bring MSELECT out of reset.
- write32(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr);
+ write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST);
}
@@ -459,19 +459,16 @@ static void config_mselect(void)
static void clear_cpu_resets(void)
{
// Take the non-cpu of the G and LP clusters out of reset.
- write32(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr);
- write32(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr);
+ write32(clk_rst_rst_cpulp_cmplx_clr_ptr, CLR_NONCPURESET);
+ write32(clk_rst_rst_cpug_cmplx_clr_ptr, CLR_NONCPURESET);
// Clear software controlled reset of the slow cluster.
- write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
- clk_rst_rst_cpulp_cmplx_clr_ptr);
+ write32(clk_rst_rst_cpulp_cmplx_clr_ptr,
+ CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0);
// Clear software controlled reset of the fast cluster.
- write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
- CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
- CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
- CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3,
- clk_rst_rst_cpug_cmplx_clr_ptr);
+ write32(clk_rst_rst_cpug_cmplx_clr_ptr,
+ CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3);
}
@@ -483,7 +480,8 @@ static void power_on_partition(unsigned id)
uint32_t bit = 0x1 << id;
if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
// Partition is not on. Turn it on.
- write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
+ write32(pmc_ctlr_pwrgate_toggle_ptr,
+ id | PWRGATE_TOGGLE_START);
// Wait until the partition is powerd on.
while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@@ -513,8 +511,8 @@ static void power_on_main_cpu(void)
*/
uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
- write32(orig_timer * (408000000 / 32768),
- pmc_ctlr_cpupwrgood_timer_ptr);
+ write32(pmc_ctlr_cpupwrgood_timer_ptr,
+ orig_timer * (408000000 / 32768));
if (wakeup_on_lp()) {
power_on_partition(PARTID_C1NC);
@@ -526,11 +524,11 @@ static void power_on_main_cpu(void)
}
// Give I/O signals time to stablize.
- write32(20 | EVENT_MSEC | FLOW_MODE_STOP,
- flow_ctlr_halt_cop_events_ptr);
+ write32(flow_ctlr_halt_cop_events_ptr,
+ 20 | EVENT_MSEC | FLOW_MODE_STOP);
// Restore the original PMC_CPUPWRGOOD_TIMER.
- write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
+ write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer);
}
@@ -552,17 +550,17 @@ void lp0_resume(void)
flow_ctlr_cluster_control_ptr);
// Program SUPER_CCLK_DIVIDER.
- write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
+ write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB);
config_core_sight();
config_pllu();
// Set the CPU reset vector.
- write32(get_wakeup_vector(), evp_cpu_reset_ptr);
+ write32(evp_cpu_reset_ptr, get_wakeup_vector());
// Select CPU complex clock source.
- write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
+ write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY);
config_mselect();
@@ -573,27 +571,27 @@ void lp0_resume(void)
uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
- write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
+ write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width);
// Enable the CPU complex clock.
- write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
- write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
+ write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU);
+ write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP);
clear_cpu_resets();
config_tsc();
// Disable VPR.
- write32(0, mc_video_protect_size_mb_ptr);
- write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
- mc_video_protect_reg_ctrl_ptr);
+ write32(mc_video_protect_size_mb_ptr, 0);
+ write32(mc_video_protect_reg_ctrl_ptr,
+ VIDEO_PROTECT_WRITE_ACCESS_DISABLE);
power_on_main_cpu();
// Halt the AVP.
while (1)
- write32(FLOW_MODE_STOP | EVENT_JTAG,
- flow_ctlr_halt_cop_events_ptr);
+ write32(flow_ctlr_halt_cop_events_ptr,
+ FLOW_MODE_STOP | EVENT_JTAG);
}
diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c
index 760d058..0054036 100644
--- a/src/soc/nvidia/tegra124/power.c
+++ b/src/soc/nvidia/tegra124/power.c
@@ -41,7 +41,7 @@ static void power_ungate_partition(uint32_t id)
pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
- write32(pwrgate_toggle, &pmc->pwrgate_toggle);
+ write32(&pmc->pwrgate_toggle, pwrgate_toggle);
// Wait for the request to be accepted.
while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
@@ -67,14 +67,14 @@ void power_enable_cpu_rail(void)
* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
* set it for 5ms as per SysEng (102MHz/5mS = 510000).
*/
- write32(510000, &pmc->cpupwrgood_timer);
+ write32(&pmc->cpupwrgood_timer, 510000);
power_ungate_partition(POWER_PARTID_CRAIL);
uint32_t cntrl = read32(&pmc->cntrl);
cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY;
cntrl |= PMC_CNTRL_CPUPWRREQ_OE;
- write32(cntrl, &pmc->cntrl);
+ write32(&pmc->cntrl, cntrl);
}
void power_ungate_cpu(void)
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index 8e090aa..4eca16f 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -231,7 +231,7 @@ int spi_claim_bus(struct spi_slave *slave)
else
val |= SPI_CMD1_CS_SW_VAL;
- write32(val, ®s->command1);
+ write32(®s->command1, val);
return 0;
}
@@ -247,7 +247,7 @@ void spi_release_bus(struct spi_slave *slave)
else
val &= ~SPI_CMD1_CS_SW_VAL;
- write32(val, ®s->command1);
+ write32(®s->command1, val);
}
static void dump_fifo_status(struct tegra_spi_channel *spi)
@@ -384,12 +384,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
* PIO transfers */
- write32(todo - 1, &spi->regs->dma_blk);
+ write32(&spi->regs->dma_blk, todo - 1);
if (dir == SPI_SEND) {
unsigned int to_fifo = bytes;
while (to_fifo) {
- write32(*p, &spi->regs->tx_fifo);
+ write32(&spi->regs->tx_fifo, *p);
p++;
to_fifo--;
}
@@ -496,11 +496,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* ensure bytes to send will be visible to DMA controller */
dcache_clean_by_mva(spi->out_buf, bytes);
- write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
- write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
+ write32(&spi->dma_out->regs->apb_ptr,
+ (u32)&spi->regs->tx_fifo);
+ write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf);
setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_out);
- write32(wcount, &spi->dma_out->regs->wcount);
+ write32(&spi->dma_out->regs->wcount, wcount);
} else {
spi->dma_in = dma_claim();
if (!spi->dma_in)
@@ -509,15 +510,15 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* avoid data collisions */
dcache_clean_invalidate_by_mva(spi->in_buf, bytes);
- write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
- write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
+ write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo);
+ write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf);
clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_in);
- write32(wcount, &spi->dma_in->regs->wcount);
+ write32(&spi->dma_in->regs->wcount, wcount);
}
/* BLOCK_SIZE starts at n-1 */
- write32(todo - 1, &spi->regs->dma_blk);
+ write32(&spi->regs->dma_blk, todo - 1);
return todo;
}
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index fd8074d..726278e 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -56,20 +56,19 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr)
tegra124_uart_tx_flush(uart_ptr);
// Disable interrupts.
- write8(0, &uart_ptr->ier);
+ write8(&uart_ptr->ier, 0);
// Force DTR and RTS to high.
- write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+ write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS);
// Set line configuration, access divisor latches.
- write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+ write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config);
// Set the divisor.
- write8(divisor & 0xff, &uart_ptr->dll);
- write8((divisor >> 8) & 0xff, &uart_ptr->dlm);
+ write8(&uart_ptr->dll, divisor & 0xff);
+ write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
// Hide the divisor latches.
- write8(line_config, &uart_ptr->lcr);
+ write8(&uart_ptr->lcr, line_config);
// Enable FIFOs, and clear receive and transmit.
- write8(UART8250_FCR_FIFO_EN |
- UART8250_FCR_CLEAR_RCVR |
- UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+ write8(&uart_ptr->fcr,
+ UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT);
}
static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
@@ -82,7 +81,7 @@ static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
- write8(data, &uart_ptr->thr);
+ write8(&uart_ptr->thr, data);
}
static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr)
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
index 28603ae..ae0553a 100644
--- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
@@ -189,8 +189,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
* release pad retention and retain the memory content until the
* initialization is complete.
*/
- write32(PAD_RETENTION_DRAM_COREBLK_VAL,
- &exynos_power->padret_dram_cblk_opt);
+ write32(&exynos_power->padret_dram_cblk_opt,
+ PAD_RETENTION_DRAM_COREBLK_VAL);
do {
ret = read32(&exynos_power->padret_dram_status);
} while (ret != 0x1);
diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c
index e8892cd..73daebf 100644
--- a/src/soc/samsung/exynos5420/dp_lowlevel.c
+++ b/src/soc/samsung/exynos5420/dp_lowlevel.c
@@ -56,7 +56,7 @@ static inline unsigned long fradl(void *v) {
#define lread32(a) fradl((void *)(a))
#else
-#define lwrite32(a,b) write32((unsigned long)(a), (void *)(b))
+#define lwrite32(a,b) write32((void *)(b), (unsigned long)(a))
#define lread32(a) read32((void *)(a))
#endif
diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c
index 49875d7..0dc1834 100644
--- a/src/soc/samsung/exynos5420/i2c.c
+++ b/src/soc/samsung/exynos5420/i2c.c
@@ -433,7 +433,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len)
{
while (!hsi2c_check_transfer(regs) && len) {
if (!(read32(®s->usi_fifo_stat) & Hsi2cTxFifoFull)) {
- write32(*data++, ®s->usi_txdata);
+ write32(®s->usi_txdata, *data++);
len--;
}
}
@@ -455,7 +455,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop)
{
const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster;
- write32(HSI2C_SLV_ADDR_MAS(seg->chip), ®s->i2c_addr);
+ write32(®s->i2c_addr, HSI2C_SLV_ADDR_MAS(seg->chip));
/*
* We really only want to stop after this transaction (I think) if the
@@ -468,14 +468,14 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop)
seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans;
if (seg->read) {
- write32(usi_ctl | Hsi2cRxchon, ®s->usi_ctl);
- write32(autoconf | Hsi2cReadWrite, ®s->i2c_auto_conf);
+ write32(®s->usi_ctl, usi_ctl | Hsi2cRxchon);
+ write32(®s->i2c_auto_conf, autoconf | Hsi2cReadWrite);
if (hsi2c_recvdata(regs, seg->buf, seg->len))
return -1;
} else {
- write32(usi_ctl | Hsi2cTxchon, ®s->usi_ctl);
- write32(autoconf, ®s->i2c_auto_conf);
+ write32(®s->usi_ctl, usi_ctl | Hsi2cTxchon);
+ write32(®s->i2c_auto_conf, autoconf);
if (hsi2c_senddata(regs, seg->buf, seg->len))
return -1;
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