[coreboot-gerrit] New patch to review for coreboot: 49794fe nyan*: I2C: Fix bus clear BC_TERMINATE naming.

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8152

-gerrit

commit 49794feec2139566667c2f02b2a2f22ad42032de
Author: Tom Warren <twarren at nvidia.com>
Date:   Wed Jul 2 09:25:35 2014 -0700

    nyan*: I2C: Fix bus clear BC_TERMINATE naming.
    
    In the original fix for the 'Lost arb' we were seeing on
    Nyan* during reboot stress testing, I had the name of
    BC_TERMINATE's bit setting wrong. Fix this to use the
    IMMEDIATE (1) setting. The setting didn't change, just
    the name. According to Julius this is the optimal
    setting for bus clear in this instance. Also widened
    the SCLK_THRESHOLD mask to 8 bits as per spec.
    
    BUG=chrome-os-partner:28323
    BRANCH=nyan
    TEST=Tested on nyan. Built for nyan and nyan_big.
    
    Original-Change-Id: I19588690924b83431d9f4d3d2eb64f4947849a33
    Original-Signed-off-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/206409
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    (cherry picked from commit 76e08d0cb0fb87e2c75d3086930f272b645ecf4e)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: If187ddf53660feaceab96efe44a3aadad60c43ff
---
 src/soc/nvidia/tegra/i2c.c | 4 ++--
 src/soc/nvidia/tegra/i2c.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index 542d4f0..6f9142c 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -37,9 +37,9 @@ static void do_bus_clear(int bus)
 	// 1. Reset the I2C controller (already done)
 	// 2. Set the # of clock pulses required (using default of 9)
 	// 3. Select STOP condition (using default of 1 = STOP)
-	// 4. Set TERMINATE condition (1 = THRESHOLD)
+	// 4. Set TERMINATE condition (1 = IMMEDIATE)
 	bc = read32(&regs->bus_clear_config);
-	bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD;
+	bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE;
 	write32(bc, &regs->bus_clear_config);
 	// 4.1 Set MSTR_CONFIG_LOAD and wait for clear
 	write32(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h
index 4b1bddd..9d7de14 100644
--- a/src/soc/nvidia/tegra/i2c.h
+++ b/src/soc/nvidia/tegra/i2c.h
@@ -115,9 +115,9 @@ enum {
 enum {
 	I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT = 16,
 	I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_MASK =
-		0x7f << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT,
+		0xff << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT,
 	I2C_BUS_CLEAR_CONFIG_BC_STOP_COND_STOP = 0x1 << 2,
-	I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD = 0x1 << 1,
+	I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE = 0x1 << 1,
 	I2C_BUS_CLEAR_CONFIG_BC_ENABLE = 0x1 << 0,
 
 	I2C_BUS_CLEAR_STATUS_CLEARED = 0x1 << 0,