[coreboot-gerrit] Patch set updated for coreboot: 54ce059 northbridge: Drop print_ implementation from non-romcc boards
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Tue Jan 6 18:22:15 CET 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7856
-gerrit
commit 54ce0596cbe8ce43fdd557603a53150a6a5ad9a3
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Mon Jan 5 12:59:54 2015 -0800
northbridge: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
src/northbridge/amd/amdfam10/amdfam10.h | 7 +-
src/northbridge/amd/amdfam10/debug.c | 26 ++--
src/northbridge/amd/amdfam10/raminit_amdmct.c | 6 +-
src/northbridge/amd/amdfam10/setup_resource_map.c | 20 +--
src/northbridge/amd/amdk8/coherent_ht.c | 32 ++--
src/northbridge/amd/amdk8/debug.c | 22 +--
src/northbridge/amd/amdk8/f.h | 7 +-
src/northbridge/amd/amdk8/incoherent_ht.c | 10 +-
src/northbridge/amd/amdk8/raminit_test.c | 29 +---
src/northbridge/amd/amdmct/mct/mct_d.c | 2 +-
src/northbridge/amd/amdmct/mct/mctdqs_d.c | 14 +-
src/northbridge/amd/amdmct/mct/mctsrc.c | 20 +--
src/northbridge/amd/amdmct/mct/mcttmrl.c | 7 +-
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 14 +-
src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 7 +-
src/northbridge/amd/gx2/raminit.c | 2 +-
src/northbridge/amd/lx/raminit.c | 30 ++--
src/northbridge/dmp/vortex86ex/raminit.c | 12 +-
src/northbridge/intel/e7501/debug.c | 135 +++-------------
src/northbridge/intel/e7501/raminit.c | 18 +--
src/northbridge/intel/e7505/debug.c | 135 +++-------------
src/northbridge/intel/e7505/raminit.c | 18 +--
src/northbridge/intel/i3100/raminit.c | 27 ++--
src/northbridge/intel/i3100/raminit_ep80579.c | 180 ++++++----------------
src/northbridge/intel/i440bx/debug.c | 26 +---
src/northbridge/intel/i440bx/raminit.c | 8 +-
src/northbridge/intel/i440lx/raminit.c | 8 +-
src/northbridge/intel/i82810/debug.c | 47 ++----
src/northbridge/intel/i855/debug.c | 66 +++-----
src/northbridge/intel/i855/raminit.c | 24 +--
src/northbridge/intel/i945/debug.c | 4 +-
src/northbridge/via/cn700/raminit.c | 8 +-
src/northbridge/via/cn700/vga.c | 2 +-
src/northbridge/via/cx700/early_smbus.c | 38 ++---
src/northbridge/via/cx700/raminit.c | 36 ++---
src/northbridge/via/vx800/early_smbus.c | 50 +++---
src/northbridge/via/vx800/raminit.c | 8 +-
src/northbridge/via/vx900/chrome9hd.c | 6 +-
src/northbridge/via/vx900/early_smbus.c | 6 +-
src/northbridge/via/vx900/early_vx900.c | 6 +-
src/northbridge/via/vx900/lpc.c | 2 +-
src/northbridge/via/vx900/northbridge.c | 12 +-
src/northbridge/via/vx900/pcie.c | 4 +-
src/northbridge/via/vx900/raminit_ddr3.c | 2 +-
src/northbridge/via/vx900/sata.c | 47 +++---
45 files changed, 387 insertions(+), 803 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index d292306..ab4b42e 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1147,11 +1147,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __PRE_RAM__
- print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
-#else
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
-#endif
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
case 1: //trained
@@ -1164,11 +1160,10 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
}
if(needs_reset) {
+ printk(BIOS_DEBUG, "mem trained failed\n");
#ifdef __PRE_RAM__
- print_debug("mem trained failed\n");
soft_reset();
#else
- printk(BIOS_DEBUG, "mem trained failed\n");
hard_reset();
#endif
}
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 7d00af7..d1fdaf8 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -108,7 +108,7 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
val >>= 8;
}
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static void dump_pci_device(u32 dev)
@@ -122,7 +122,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
int i;
int end = start + size;
print_debug_pci_dev(dev);
- print_debug(" -- index_reg="); print_debug_hex32(index_reg);
+ printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg);
for(i = start; i < end; i++) {
u32 val;
@@ -135,7 +135,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
}
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg)
@@ -151,7 +151,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
int i;
print_debug_pci_dev(dev);
- print_debug(" index reg: "); print_debug_hex16(index_reg); print_debug(" type: "); print_debug_hex8(type);
+ printk(BIOS_DEBUG, " index reg: %04x type: %02x", index_reg, type);
type<<=28;
@@ -163,7 +163,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
val = pci_read_config32_index(dev, index_reg, i|type);
printk(BIOS_DEBUG, " %08x", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_devices(void)
@@ -221,7 +221,7 @@ static inline void dump_pci_devices_on_bus(u32 busn)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
u32 device;
device = ctrl->spd_addr[i];
@@ -241,7 +241,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->spd_addr[i+DIMM_SOCKETS];
if (device) {
@@ -260,14 +260,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
static void dump_smbus_registers(void)
{
u32 device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -285,7 +285,7 @@ static void dump_smbus_registers(void)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
@@ -303,7 +303,7 @@ static inline void dump_io_resources(u32 port)
val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -312,12 +312,12 @@ static inline void dump_io_resources(u32 port)
static inline void dump_mem(u32 start, u32 end)
{
u32 i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index e5c18a8..6b02209 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -219,7 +219,7 @@ u32 mctGetLogicalCPUID(u32 Node)
break;
default:
/* FIXME: mabe we should die() here. */
- print_err("FIXME! CPU Version unknown or not supported! \n");
+ printk(BIOS_ERR, "FIXME! CPU Version unknown or not supported! \n");
ret = 0;
}
@@ -237,9 +237,9 @@ static void raminit_amdmct(struct sys_info *sysinfo)
struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
- print_debug("raminit_amdmct begin:\n");
+ printk(BIOS_DEBUG, "raminit_amdmct begin:\n");
mctAutoInitMCT_D(pMCTstat, pDCTstatA);
- print_debug("raminit_amdmct end:\n");
+ printk(BIOS_DEBUG, "raminit_amdmct end:\n");
}
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index 2eeca44..ca7f964 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -23,7 +23,7 @@
static void setup_resource_map(const u32 *register_values, u32 max)
{
u32 i;
-// print_debug("setting up resource map....");
+// printk(BIOS_DEBUG, "setting up resource map....");
for(i = 0; i < max; i += 3) {
device_t dev;
@@ -37,14 +37,14 @@ static void setup_resource_map(const u32 *register_values, u32 max)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
-// print_debug("done.\n");
+// printk(BIOS_DEBUG, "done.\n");
}
void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
{
u32 i;
-// print_debug("setting up resource map offset....");
+// printk(BIOS_DEBUG, "setting up resource map offset....");
for(i = 0; i < max; i += 3) {
device_t dev;
u32 where;
@@ -56,7 +56,7 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p
reg |= register_values[i+2] + offset_io_base;
pci_write_config32(dev, where, reg);
}
-// print_debug("done.\n");
+// printk(BIOS_DEBUG, "done.\n");
}
#define RES_PCI_IO 0x10
@@ -69,12 +69,12 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
u32 i;
#if RES_DEBUG
- print_debug("setting up resource map ex offset....");
+ printk(BIOS_DEBUG, "setting up resource map ex offset....");
#endif
#if RES_DEBUG
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
@@ -127,7 +127,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
}
#if RES_DEBUG
- print_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
}
@@ -136,11 +136,11 @@ void setup_resource_map_x(const u32 *register_values, u32 max)
u32 i;
#if RES_DEBUG
- print_debug("setting up resource map ex offset....");
+ printk(BIOS_DEBUG, "setting up resource map ex offset....");
#endif
#if RES_DEBUG
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
@@ -189,7 +189,7 @@ void setup_resource_map_x(const u32 *register_values, u32 max)
}
#if RES_DEBUG
- print_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
}
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 8abb31f..a8d8700 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -145,7 +145,7 @@ static void disable_probes(void)
u32 val;
- print_spew("Disabling read/write/fill probes for UP... ");
+ printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... ");
val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
@@ -153,7 +153,7 @@ static void disable_probes(void)
HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
- print_spew("done.\n");
+ printk(BIOS_SPEW, "done.\n");
}
@@ -199,14 +199,13 @@ static void enable_routing(u8 node)
*/
/* Enable routing table */
- print_spew("Enabling routing table for node ");
- print_spew_hex8(node);
+ printk(BIOS_SPEW, "Enabling routing table for node %d", node);
val=pci_read_config32(NODE_HT(node), 0x6c);
val &= ~((1<<1)|(1<<0));
pci_write_config32(NODE_HT(node), 0x6c, val);
- print_spew(" done.\n");
+ printk(BIOS_SPEW, " done.\n");
}
#if CONFIG_MAX_PHYSICAL_CPUS > 1
@@ -230,7 +229,7 @@ static u8 link_to_register(int ldt)
if (ldt&0x02) return 0x00;
/* we should never get here */
- print_spew("Unknown Link\n");
+ printk(BIOS_SPEW, "Unknown Link\n");
return 0;
}
@@ -248,15 +247,14 @@ static void rename_temp_node(u8 node)
{
uint32_t val;
- print_spew("Renaming current temporary node to ");
- print_spew_hex8(node);
+ printk(BIOS_SPEW, "Renaming current temporary node to %d", node);
val=pci_read_config32(NODE_HT(7), 0x60);
val &= (~7); /* clear low bits. */
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
- print_spew(" done.\n");
+ printk(BIOS_SPEW, " done.\n");
}
static int verify_connection(u8 dest)
@@ -514,7 +512,7 @@ static void setup_remote_node(u8 node)
};
int i;
- print_spew("setup_remote_node: ");
+ printk(BIOS_SPEW, "setup_remote_node: ");
/* copy the default resource map from node 0 */
for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
@@ -525,7 +523,7 @@ static void setup_remote_node(u8 node)
pci_write_config32(NODE_MP(7), reg, value);
}
- print_spew("done\n");
+ printk(BIOS_SPEW, "done\n");
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
@@ -664,7 +662,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
static void setup_uniprocessor(void)
{
- print_spew("Enabling UP settings\n");
+ printk(BIOS_SPEW, "Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return;
@@ -1491,7 +1489,7 @@ static unsigned setup_smp(void)
{
unsigned nodes;
- print_spew("Enabling SMP settings\n");
+ printk(BIOS_SPEW, "Enabling SMP settings\n");
nodes = setup_smp2();
#if CONFIG_MAX_PHYSICAL_CPUS > 2
@@ -1528,14 +1526,14 @@ static unsigned verify_mp_capabilities(unsigned nodes)
#if CONFIG_MAX_PHYSICAL_CPUS > 2
case 0x02: /* MPCap */
if(nodes > 2) {
- print_err("Going back to DP\n");
+ printk(BIOS_ERR, "Going back to DP\n");
return 2;
}
break;
#endif
case 0x00: /* Non SMP */
if(nodes >1 ) {
- print_err("Going back to UP\n");
+ printk(BIOS_ERR, "Going back to UP\n");
return 1;
}
break;
@@ -1613,7 +1611,7 @@ static void coherent_ht_finalize(unsigned nodes)
* registers on Hammer A0 revision.
*/
- print_spew("coherent_ht_finalize\n");
+ printk(BIOS_SPEW, "coherent_ht_finalize\n");
#if !CONFIG_K8_REV_F_SUPPORT
rev_a0 = is_cpu_rev_a0();
#endif
@@ -1654,7 +1652,7 @@ static void coherent_ht_finalize(unsigned nodes)
#endif
}
- print_spew("done\n");
+ printk(BIOS_SPEW, "done\n");
}
static int apply_cpu_errata_fixes(unsigned nodes)
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index 4f9d8ca..c1021e5 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -54,7 +54,7 @@ static void dump_pci_device(unsigned dev)
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#if CONFIG_K8_REV_F_SUPPORT
@@ -63,7 +63,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
{
int i;
print_debug_pci_dev(dev);
- print_debug(" -- index_reg="); print_debug_hex32(index_reg);
+ printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg);
for(i = 0; i < 0x40; i++) {
uint32_t val;
@@ -76,7 +76,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
}
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
@@ -135,7 +135,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
@@ -155,7 +155,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
@@ -174,14 +174,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
static void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -199,7 +199,7 @@ static void dump_smbus_registers(void)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
@@ -218,7 +218,7 @@ static inline void dump_io_resources(unsigned port)
val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -227,13 +227,13 @@ static inline void dump_io_resources(unsigned port)
static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index bfeee0e..4f958c5 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -564,11 +564,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __PRE_RAM__
- print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
-#else
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
-#endif
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
case 1: //trained
@@ -581,11 +577,10 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
}
if(needs_reset) {
+ printk(BIOS_DEBUG, "mem trained failed\n");
#ifdef __PRE_RAM__
- print_debug("mem trained failed\n");
soft_reset();
#else
- printk(BIOS_DEBUG, "mem trained failed\n");
hard_reset();
#endif
}
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index cf8ad52..3c6cf33 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -342,7 +342,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
if (ctrl & ((1 << 4) | (1 << 8))) {
- print_err("Detected error on Hypertransport Link\n");
+ printk(BIOS_ERR, "Detected error on Hypertransport Link\n");
break;
}
}
@@ -362,10 +362,10 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
pos = ht_lookup_slave_capability(dev);
if (!pos) {
- print_err("udev="); print_err_hex32(udev);
- print_err("\tupos="); print_err_hex32(upos);
- print_err("\tuoffs="); print_err_hex32(uoffs);
- print_err("\tHT link capability not found\n");
+ printk(BIOS_ERR, "udev=%08x", udev);
+ printk(BIOS_ERR, "\tupos=%08x", upos);
+ printk(BIOS_ERR, "\tuoffs=%08x", uoffs);
+ printk(BIOS_ERR, "\tHT link capability not found\n");
break;
}
diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c
index fd2107c..be46f27 100644
--- a/src/northbridge/amd/amdk8/raminit_test.c
+++ b/src/northbridge/amd/amdk8/raminit_test.c
@@ -57,11 +57,7 @@ static uint32_t pci_read_config32(device_t dev, unsigned where)
(pci_register[addr + 3] << 24);
#if 0
- print_debug("pcir32(");
- print_debug_hex32(addr);
- print_debug("):");
- print_debug_hex32(value);
- print_debug("\n");
+ printk(BIOS_DEBUG, "pcir32(%08x): %08x\n", addr, value);
#endif
return value;
@@ -92,11 +88,7 @@ static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
pci_register[addr + 3] = (value >> 24) & 0xff;
#if 0
- print_debug("pciw32(");
- print_debug_hex32(addr);
- print_debug(", ");
- print_debug_hex32(value);
- print_debug(")\n");
+ printk(BIOS_DEBUG, "pciw32(%08x, %08x)\n", addr, value);
#endif
}
@@ -285,13 +277,8 @@ static int spd_read_byte(unsigned device, unsigned address)
}
}
#if 0
- print_debug("spd_read_byte(");
- print_debug_hex32(device);
- print_debug(", ");
- print_debug_hex32(address);
- print_debug(") -> ");
- print_debug_hex32(result);
- print_debug("\n");
+ printk(BIOS_DEBUG, "spd_read_byte(%08x, %08x) -> %08x\n",
+ device, address, result);
#endif
if (spd_count >= spd_fail_count) {
result = -1;
@@ -392,9 +379,7 @@ static void test1(void)
raminit_main();
#if 0
- print_debug("spd_count: ");
- print_debug_hex32(spd_count);
- print_debug("\n");
+ printk(BIOS_DEBUG, "spd_count: %d\n", spd_count);
#endif
}
@@ -410,9 +395,7 @@ static void do_test2(int i)
reset_tests();
spd_fail_count = i;
- print_debug("\nSPD will fail after: ");
- print_debug_hex32(spd_fail_count);
- print_debug(" accesses.\n");
+ printk(BIOS_DEBUG, "\nSPD will fail after: %d accesses.\n", %d);
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 924c5fb..7c7550d 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -262,7 +262,7 @@ restartinit:
node_sys_base += (pDCTstat->NodeSysLimit + 2) & ~0x0F;
}
if (NodesWmem == 0) {
- print_debug("No Nodes?!\n");
+ printk(BIOS_DEBUG, "No Nodes?!\n");
goto fatalexit;
}
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 17fb289..d7fd738 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -357,22 +357,20 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
for (Dir = 0; Dir < 2; Dir++) {
if (Dir == 0) {
- print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n");
+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n");
} else {
- print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n");
+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n");
}
for (Channel = 0; Channel < 2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x\n", Channel);
for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) {
- print_debug("\t\tReceiver:"); print_debug_hex8(Receiver);
+ printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver);
p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir];
- print_debug(": ");
for (i=0;i<8; i++) {
val = p[i];
- print_debug_hex8(val);
- print_debug(" ");
+ printk(BIOS_DEBUG, "%02x ", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index feb4170..9c1324d 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -459,12 +459,9 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
#if DQS_TRAIN_DEBUG > 0
{
u8 Channel;
- print_debug("TrainRcvrEn: CH_MaxRdLat:\n");
+ printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n");
for(Channel = 0; Channel<2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel);
- print_debug(": ");
- print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] );
- print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
}
}
#endif
@@ -476,20 +473,17 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
u8 i;
u8 *p;
- print_debug("TrainRcvrEn: CH_D_B_RCVRDLY:\n");
+ printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n");
for(Channel = 0; Channel < 2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x\n", Channel);
for(Receiver = 0; Receiver<8; Receiver+=2) {
- print_debug("\t\tReceiver:");
- print_debug_hex8(Receiver);
+ printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver);
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
- print_debug(": ");
for (i=0;i<8; i++) {
val = p[i];
- print_debug_hex8(val);
- print_debug(" ");
+ printk(BIOS_DEBUG, "%02x ", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c
index 03ebf97..d31e744 100644
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -198,12 +198,9 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
#if DQS_TRAIN_DEBUG > 0
{
u8 Channel;
- print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n");
+ printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n");
for(Channel = 0; Channel<2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel);
- print_debug(": ");
- print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] );
- print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
}
}
#endif
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index d7084ad..6a9b921 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -371,22 +371,20 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
for (Dir = 0; Dir < 2; Dir++) {
if (Dir == 1) {
- print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n");
+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n");
} else {
- print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n");
+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n");
}
for (Channel = 0; Channel < 2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x\n", Channel);
for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) {
- print_debug("\t\tReceiver:"); print_debug_hex8(Receiver);
+ printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver);
p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir];
- print_debug(": ");
for (i=0;i<8; i++) {
val = p[i];
- print_debug_hex8(val);
- print_debug(" ");
+ printk(BIOS_DEBUG, "%02x ", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
index c7e1352..ec8df9a 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
@@ -192,12 +192,9 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
#if DQS_TRAIN_DEBUG > 0
{
u8 Channel;
- print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n");
+ printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n");
for(Channel = 0; Channel<2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel);
- print_debug(": ");
- print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] );
- print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
}
}
#endif
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index d9af161..fd872b3 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -606,6 +606,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
*ptr = (unsigned long)i;
}
- print_info("RAM DLL lock\n");
+ printk(BIOS_INFO, "RAM DLL lock\n");
}
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 7c95ab4..d8515c6 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -38,13 +38,13 @@ static void banner(const char *s)
static void __attribute__((noreturn)) hcf(void)
{
- print_emerg("DIE\n");
+ printk(BIOS_EMERG, "DIE\n");
/* this guarantees we flush the UART fifos (if any) and also
* ensures that things, in general, keep going so no debug output
* is lost
*/
while (1)
- print_emerg_char(0);
+ printk(BIOS_EMERG, "%c", 0);
}
static void auto_size_dimm(unsigned int dimm)
@@ -67,7 +67,7 @@ static void auto_size_dimm(unsigned int dimm)
/* EEPROM byte usage: (5) Number of DIMM Banks */
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
- print_emerg("Number of module banks not compatible\n");
+ printk(BIOS_EMERG, "Number of module banks not compatible\n");
post_code(ERROR_BANK_SET);
hcf();
}
@@ -78,7 +78,7 @@ static void auto_size_dimm(unsigned int dimm)
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
- print_emerg("Number of device banks not compatible\n");
+ printk(BIOS_EMERG, "Number of device banks not compatible\n");
post_code(ERROR_BANK_SET);
hcf();
}
@@ -94,7 +94,7 @@ static void auto_size_dimm(unsigned int dimm)
*/
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
- print_emerg("Assymetirc DIMM not compatible\n");
+ printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
@@ -111,7 +111,7 @@ static void auto_size_dimm(unsigned int dimm)
dimm_size = __builtin_ctz(dimm_size);
banner("TEST DIMM SIZE>8");
if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
- print_emerg("Only support up to 1 GB per DIMM\n");
+ printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
post_code(ERROR_DENSITY_DIMM);
hcf();
}
@@ -144,7 +144,7 @@ static void auto_size_dimm(unsigned int dimm)
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
banner("MAXCOLADDR");
if (spd_byte > MAX_COL_ADDR) {
- print_emerg("DIMM page size not compatible\n");
+ printk(BIOS_EMERG, "DIMM page size not compatible\n");
post_code(ERROR_SET_PAGE);
hcf();
}
@@ -186,7 +186,7 @@ static void checkDDRMax(void)
/* I don't think you need this check.
if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
- print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+ printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
post_code(POST_PLL_MEM_FAIL);
hcf();
} */
@@ -201,7 +201,7 @@ static void checkDDRMax(void)
/* current speed > max speed? */
if (GeodeLinkSpeed() > speed) {
- print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+ printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
post_code(POST_PLL_MEM_FAIL);
hcf();
}
@@ -319,7 +319,7 @@ static void setCAS(void)
} else if ((casmap0 &= casmap1)) {
spd_byte = CASDDR[__builtin_ctz(casmap0)];
} else {
- print_emerg("DIMM CAS Latencies not compatible\n");
+ printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
post_code(ERROR_DIFF_DIMMS);
hcf();
}
@@ -513,7 +513,7 @@ static void EnableMTest(void)
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(MC_CFCLK_DBUG, msr);
- print_info("Enabled MTest for TLA debug\n");
+ printk(BIOS_INFO, "Enabled MTest for TLA debug\n");
}
#endif
@@ -558,14 +558,14 @@ void sdram_set_spd_registers(const struct mem_controller *ctrl)
banner("Check DIMM 0");
/* Check DIMM is not Register and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- print_emerg("DIMM0 NOT COMPATIBLE\n");
+ printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
banner("Check DIMM 1");
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- print_emerg("DIMM1 NOT COMPATIBLE\n");
+ printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
@@ -633,7 +633,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr = rdmsr(MC_CF07_DATA);
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
- print_emerg("No memory in the system\n");
+ printk(BIOS_EMERG, "No memory in the system\n");
post_code(ERROR_NO_DIMMS);
hcf();
}
@@ -775,6 +775,6 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo |= 1;
wrmsr(msrnum, msr);
}
- print_info("RAM DLL lock\n");
+ printk(BIOS_INFO, "RAM DLL lock\n");
}
diff --git a/src/northbridge/dmp/vortex86ex/raminit.c b/src/northbridge/dmp/vortex86ex/raminit.c
index 2382fe2..227b376 100644
--- a/src/northbridge/dmp/vortex86ex/raminit.c
+++ b/src/northbridge/dmp/vortex86ex/raminit.c
@@ -258,17 +258,17 @@ static u8 detect_ddr3_dram_size(void)
static void print_ddr3_memory_setup(void)
{
#if CONFIG_DEBUG_RAM_SETUP
- print_debug("DDR3 Timing Reg 0-3:\n");
- print_debug("NB 6e : ");
+ printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n");
+ printk(BIOS_DEBUG, "NB 6e : ");
print_debug_hex16(pci_read_config16(NB, 0x6e));
- print_debug("\nNB 74 : ");
+ printk(BIOS_DEBUG, "\nNB 74 : ");
print_debug_hex32(pci_read_config32(NB, 0x74));
- print_debug("\nNB 78 : ");
+ printk(BIOS_DEBUG, "\nNB 78 : ");
print_debug_hex32(pci_read_config32(NB, 0x78));
- print_debug("\nNB 7c : ");
+ printk(BIOS_DEBUG, "\nNB 7c : ");
print_debug_hex32(pci_read_config32(NB, 0x7c));
u16 mbr = pci_read_config16(NB, 0x6c);
- print_debug("\nNB 6c(MBR) : ");
+ printk(BIOS_DEBUG, "\nNB 6c(MBR) : ");
print_debug_hex16(mbr);
const char *s;
u8 col = get_ddr3_mem_reg_col(mbr);
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index 07f1596..32a1428 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -5,12 +5,8 @@
#if 1
static void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
}
static inline void print_pci_devices(void)
@@ -27,7 +23,7 @@ static inline void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -38,24 +34,12 @@ static void dump_pci_device(unsigned dev)
for(i = 0; i < 256; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
-#else
- print_debug("\n");
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = pci_read_config8(dev, i);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_devices(void)
@@ -95,98 +79,55 @@ static inline void dump_pci_devices_on_bus(unsigned busn)
static inline void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
static inline void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "smbus: %02x", device);
-#else
- print_debug("smbus: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
@@ -194,24 +135,12 @@ static inline void dump_smbus_registers(void)
if (status < 0) {
break;
}
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -219,31 +148,15 @@ static inline void dump_io_resources(unsigned port)
{
int i;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%04x:\n", port);
-#else
- print_debug_hex16(port);
- print_debug(":\n");
-#endif
for(i=0;i<256;i++) {
uint8_t val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
-#else
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = inb(port);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x",val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -252,24 +165,12 @@ static inline void dump_io_resources(unsigned port)
static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
-#if !defined(__ROMCC__)
+ if((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
-#else
- print_debug("\n");
- print_debug_hex32(i);
- print_debug(":");
-#endif
- }
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
-#else
- print_debug(" ");
- print_debug_hex8((unsigned char)*((unsigned char *)i));
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index 2247a25..22d1bbc 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -27,9 +27,9 @@ Definitions:
//#define VALIDATE_DIMM_COMPATIBILITY
#if CONFIG_DEBUG_RAM_SETUP
-#define RAM_DEBUG_MESSAGE(x) print_debug(x)
-#define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
-#define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
+#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
+#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
+#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define RAM_DEBUG_MESSAGE(x)
@@ -784,7 +784,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
@@ -812,11 +812,11 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// Made it through all the checks, this DIMM pair is usable
dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
} else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -1523,13 +1523,13 @@ static void configure_e7501_dram_controller_mode(const struct
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -1961,7 +1961,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index 3d6ca2a..cdf6e7e 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -15,12 +15,8 @@
void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
}
void print_pci_devices(void)
@@ -37,7 +33,7 @@ void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -48,24 +44,12 @@ void dump_pci_device(unsigned dev)
for(i = 0; i < 256; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
-#else
- print_debug("\n");
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = pci_read_config8(dev, i);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
void dump_pci_devices(void)
@@ -105,98 +89,55 @@ void dump_pci_devices_on_bus(unsigned busn)
void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( spd_read_byte(device, 0) < 0 ) continue;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "smbus: %02x", device);
-#else
- print_debug("smbus: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
@@ -204,24 +145,12 @@ void dump_smbus_registers(void)
if (status < 0) {
break;
}
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -229,31 +158,15 @@ void dump_io_resources(unsigned port)
{
int i;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%04x:\n", port);
-#else
- print_debug_hex16(port);
- print_debug(":\n");
-#endif
for(i=0;i<256;i++) {
uint8_t val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
-#else
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = inb(port);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x",val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -262,23 +175,11 @@ void dump_io_resources(unsigned port)
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
-#if !defined(__ROMCC__)
+ if((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
-#else
- print_debug("\n");
- print_debug_hex32(i);
- print_debug(":");
-#endif
- }
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
-#else
- print_debug(" ");
- print_debug_hex8((unsigned char)*((unsigned char *)i));
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 909e740..b758c61 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -42,9 +42,9 @@ Definitions:
//#define VALIDATE_DIMM_COMPATIBILITY
#if CONFIG_DEBUG_RAM_SETUP
-#define RAM_DEBUG_MESSAGE(x) print_debug(x)
-#define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
-#define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
+#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
+#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
+#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
#define DUMPNORTH() dump_pci_device(MCHDEV)
#else
#define RAM_DEBUG_MESSAGE(x)
@@ -605,7 +605,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
@@ -633,11 +633,11 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// Made it through all the checks, this DIMM pair is usable
dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
} else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -1379,13 +1379,13 @@ static void configure_e7501_dram_controller_mode(const struct
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -1767,7 +1767,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 4f5a989..ebe137b 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -78,7 +78,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\n");
+ printk(BIOS_SPEW, "done.\n");
}
struct dimm_size {
@@ -610,7 +610,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\n");
+ printk(BIOS_ERR, "No memory for this cpu\n");
return;
}
return;
@@ -686,9 +686,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
die("Error - First dimm slot empty\n");
}
- print_debug("ODT Value = ");
- print_debug_hex32(data32);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT Value = %08x\n", data32);
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
@@ -916,11 +914,8 @@ static void set_receive_enable(const struct mem_controller *ctrl)
}
}
- print_debug("Receive enable A = ");
- print_debug_hex32(recena);
- print_debug(", Receive enable B = ");
- print_debug_hex32(recenb);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Receive enable A = %08x, Receive enable B = %08x\n",
+ recena, recenb);
/* clear out the calibration area */
write32(MCBAR+DCALDATA+(16*4), 0x00000000);
@@ -972,7 +967,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\n");
+ printk(BIOS_DEBUG, "Starting SDRAM Enable\n");
/* 0x80 */
pci_write_config32(ctrl->f0, DRM,
@@ -1013,9 +1008,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
for(i=0;i<8;i+=2) { /* loop through each dimm to test */
- print_debug("DIMM ");
- print_debug_hex8(i);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DIMM %08x\n", i);
/* Apply NOP */
do_delay();
@@ -1158,7 +1151,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(MCBAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\n");
+ printk(BIOS_DEBUG, "Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(MCBAR+DCALDATA+i, 0x00000000);
}
@@ -1174,13 +1167,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\n");
+ printk(BIOS_DEBUG, "Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\n");
+ printk(BIOS_DEBUG, "Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index cff7879..b2858e4 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -128,13 +128,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
sz.side1 = 0;
sz.side2 = 0;
out:
- print_debug("dimm ");
- print_debug_hex8(device);
- print_debug(" size = ");
- print_debug_hex8(sz.side1);
- print_debug(".");
- print_debug_hex8(sz.side2);
- print_debug("\n");
+ printk(BIOS_DEBUG, "dimm %02x size = %02x.%02x\n", device, sz.side1, sz.side2);
return sz;
}
@@ -165,25 +159,19 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)
pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
}
}
- print_debug("DRB = ");
- print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRB = %08x\n", pci_read_config32(ctrl->f0, DRB));
cum >>= 1;
/* set TOM top of memory */
pci_write_config16(ctrl->f0, TOM, cum);
- print_debug("TOM = ");
- print_debug_hex16(cum);
- print_debug("\n");
+ printk(BIOS_DEBUG, "TOM = %04x\n", cum);
/* set TOLM top of low memory */
if (cum > 0x18) {
cum = 0x18;
}
cum <<= 11;
pci_write_config16(ctrl->f0, TOLM, cum);
- print_debug("TOLM = ");
- print_debug_hex16(cum);
- print_debug("\n");
+ printk(BIOS_DEBUG, "TOLM = %04x\n", cum);
return 0;
}
@@ -198,11 +186,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl)
device = ctrl->channel0[i];
if (device) {
byte = spd_read_byte(device, SPD_MEMORY_TYPE);
- print_debug("spd ");
- print_debug_hex8(device);
- print_debug(" = ");
- print_debug_hex8(byte);
- print_debug("\n");
+ printk(BIOS_DEBUG, "spd %02x = %02x\n", device, byte);
if (byte == 8) {
dimm_mask |= (1 << i);
}
@@ -245,11 +229,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
if ((value & 0xff) == 0) die("Invalid # of banks\n");
reg += log2(value & 0xff);
- print_debug("dimm ");
- print_debug_hex8(i);
- print_debug(" reg = ");
- print_debug_hex8(reg);
- print_debug("\n");
+ printk(BIOS_DEBUG, "dimm %02x reg = %02x\n", i, reg);
/* set device density */
dra |= ((31-reg));
@@ -266,11 +246,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS);
dra |= ((value & 0x1) << 17);
- print_debug("DRA");
- print_debug_hex8(i);
- print_debug(" = ");
- print_debug_hex32(dra);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRA%02x = %08x\n", i, dra);
pci_write_config32(ctrl->f0, DRA + (i*4), dra);
}
@@ -321,9 +297,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
cl = 6;
else
die("CAS latency mismatch\n");
- print_debug("cl = ");
- print_debug_hex8(cl);
- print_debug("\n");
+ printk(BIOS_DEBUG, "cl = %02x\n", cl);
ci = cycle[index];
@@ -347,12 +321,8 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
if (trfc < val)
trfc = val;
}
- print_debug("trc = ");
- print_debug_hex8(trc);
- print_debug("\n");
- print_debug("trfc = ");
- print_debug_hex8(trfc);
- print_debug("\n");
+ printk(BIOS_DEBUG, "trc = %02x\n", trc);
+ printk(BIOS_DEBUG, "trfc = %02x\n", trfc);
/* Tras, Trtp, Twtr in cycles */
for (i = 0; i < DIMM_SOCKETS; i++) {
@@ -372,40 +342,26 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
if (twtr < val)
twtr = val;
}
- print_debug("tras = ");
- print_debug_hex8(tras);
- print_debug("\n");
- print_debug("trtp = ");
- print_debug_hex8(trtp);
- print_debug("\n");
- print_debug("twtr = ");
- print_debug_hex8(twtr);
- print_debug("\n");
+ printk(BIOS_DEBUG, "tras = %02x\n", tras);
+ printk(BIOS_DEBUG, "trtp = %02x\n", trtp);
+ printk(BIOS_DEBUG, "twtr = %02x\n", twtr);
val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
| ((cl - 3) << 6) | ((cl - 3) << 3));
- print_debug("drt0 = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "drt0 = %08x\n", val);
pci_write_config32(ctrl->f0, DRT0, val);
val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
| (twtr << 15));
- print_debug("drt1 = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "drt1 = %08x\n", val);
pci_write_config32(ctrl->f0, DRT1, val);
val = (magic[index]);
- print_debug("magic = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "magic = %08x\n", val);
pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
val = (mrs[index] | (cl << 20));
- print_debug("mrs = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "mrs = %08x\n", val);
return val;
}
@@ -432,9 +388,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
if (value > cycle)
cycle = value;
}
- print_debug("cycle = ");
- print_debug_hex8(cycle);
- print_debug("\n");
+ printk(BIOS_DEBUG, "cycle = %02x\n", cycle);
drc |= (1 << 20); /* enable ECC */
drc |= (3 << 30); /* enable CKE on each DIMM */
@@ -443,45 +397,40 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
/* TODO check: */
/* set front side bus speed */
msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */
- print_debug("MSR FSB_FREQ(0xcd) = ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MSR FSB_FREQ(0xcd) = %08x%08x\n", msr.hi, msr.lo);
/* TODO check that this msr really indicates fsb speed! */
if (msr.lo & 0x07) {
- print_info("533 MHz FSB\n");
+ printk(BIOS_INFO, "533 MHz FSB\n");
if (cycle <= 0x25) {
drc |= 0x5;
- print_info("400 MHz DDR\n");
+ printk(BIOS_INFO, "400 MHz DDR\n");
} else if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\n");
+ printk(BIOS_INFO, "333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x4;
- print_info("266 MHz DDR\n");
+ printk(BIOS_INFO, "266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\n");
+ printk(BIOS_INFO, "200 MHz DDR\n");
}
}
else {
- print_info("400 MHz FSB\n");
+ printk(BIOS_INFO, "400 MHz FSB\n");
if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\n");
+ printk(BIOS_INFO, "333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x0;
- print_info("266 MHz DDR\n");
+ printk(BIOS_INFO, "266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\n");
+ printk(BIOS_INFO, "200 MHz DDR\n");
}
}
- print_debug("DRC = ");
- print_debug_hex32(drc);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRC = %08x\n", drc);
return drc;
}
@@ -493,7 +442,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the SPD */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\n");
+ printk(BIOS_ERR, "No memory for this cpu\n");
return;
}
return;
@@ -520,16 +469,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x00002010;
}
- print_debug("ODT Value = ");
- print_debug_hex32(data32);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT Value = %08x\n", data32);
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
for (i = 0; i < 2; i++) {
- print_debug("ODT CS");
- print_debug_hex8(i);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT CS%d\n", i);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
@@ -544,14 +489,11 @@ static void dump_dcal_regs(void)
int i;
for (i = 0x0; i < 0x2a0; i += 4) {
if ((i % 16) == 0) {
- print_debug("\n");
- print_debug_hex16(i);
- print_debug(": ");
+ printk(BIOS_DEBUG, "\n%04x: ", i);
}
- print_debug_hex32(read32(BAR+i));
- print_debug(" ");
+ printk(BIOS_DEBUG, "%08x ", read32(BAR+i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
@@ -565,7 +507,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
u32 mode_reg;
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\n");
+ printk(BIOS_DEBUG, "Starting SDRAM Enable\n");
/* Set DRAM type and Front Side Bus frequency */
drc = spd_set_dram_controller_mode(ctrl, mask);
@@ -593,9 +535,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Apply NOP */
for (cs = 0; cs < 2; cs++) {
- print_debug("NOP CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "NOP CS%d\n", cs);
udelay(16);
write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
@@ -606,9 +546,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Apply NOP */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("NOP CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "NOP CS%d\n", cs);
write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -617,9 +555,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Precharge all banks */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("Precharge CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Precharge CS%d\n", cs);
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -629,9 +565,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* EMRS: Enable DLLs, set OCD calibration mode to default */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("EMRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "EMRS CS%d\n", cs);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -640,9 +574,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* MRS: Reset DLLs */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("MRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MRS CS%d\n", cs);
write32(BAR+DCALADDR, mode_reg);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -652,9 +584,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Precharge all banks */
udelay(48);
for (cs = 0; cs < 2; cs++) {
- print_debug("Precharge CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Precharge CS%d\n", cs);
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -665,9 +595,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (i = 0; i < 2; i++) {
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("Refresh CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Refresh CS%d\n", cs);
write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -677,9 +605,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* MRS: Set DLLs to normal */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("MRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MRS CS%d\n", cs);
write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -689,9 +615,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* EMRS: Enable DLLs */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("EMRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "EMRS CS%d\n", cs);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -712,9 +636,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Receive enable calibration */
udelay(16);
for (cs = 0; cs < 1; cs++) {
- print_debug("receive enable calibration CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "receive enable calibration CS%d\n", cs);
write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -738,18 +660,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
if (!(mask & (1<<cs)))
continue;
- print_debug("clear memory CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "clear memory CS%d\n", cs);
write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
do data32 = read32(BAR+MBCSR);
while (data32 & 0x80000000);
if (data32 & 0x40000000)
- print_debug("failed!\n");
+ printk(BIOS_DEBUG, "failed!\n");
}
/* Clear read/write FIFO pointers */
- print_debug("clear read/write fifo pointers\n");
+ printk(BIOS_DEBUG, "clear read/write fifo pointers\n");
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
udelay(16);
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
@@ -757,7 +677,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dump_dcal_regs();
- print_debug("Done\n");
+ printk(BIOS_DEBUG, "Done\n");
/* Set initialization complete */
drc |= (1 << 29);
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index ef9d513..efd4326 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -35,34 +35,18 @@ void dump_spd_registers(void)
}
}
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
void dump_pci_device(unsigned dev)
{
int i;
- print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for (i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x: %02x", i, val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index e3cfbdf..f191abe 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -752,7 +752,7 @@ static void set_dram_row_attributes(void)
PRINT_DEBUG("Found DIMM in slot %d\n", i);
if (edo && sd) {
- print_err("Mixing EDO/SDRAM unsupported!\n");
+ printk(BIOS_ERR, "Mixing EDO/SDRAM unsupported!\n");
die("HALT\n");
}
@@ -857,11 +857,11 @@ static void set_dram_row_attributes(void)
if (col == 4)
bpr |= 0xc0;
} else {
- print_err("# of banks of DIMM unsupported!\n");
+ printk(BIOS_ERR, "# of banks of DIMM unsupported!\n");
die("HALT\n");
}
if (dra == -1) {
- print_err("Page size not supported\n");
+ printk(BIOS_ERR, "Page size not supported\n");
die("HALT\n");
}
@@ -872,7 +872,7 @@ static void set_dram_row_attributes(void)
*/
struct dimm_size sz = spd_get_dimm_size(device);
if ((sz.side1 < 8)) {
- print_err("DIMMs smaller than 8MB per side\n"
+ printk(BIOS_ERR, "DIMMs smaller than 8MB per side\n"
"are not supported on this NB.\n");
die("HALT\n");
}
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 7d283a1..ddabf25 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -32,10 +32,10 @@ Macros and definitions.
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
-#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
+#define PRINT_DEBUG(x) printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG(x)
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index c3e4fb9..b74bb36 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -1,73 +1,52 @@
#include <console/console.h>
#include <arch/io.h>
#include <spd.h>
-#include "i82810.h"
#include "raminit.h"
+#include <spd.h>
+#include <console/console.h>
#if CONFIG_DEBUG_RAM_SETUP
void dump_spd_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM0 + i;
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "DIMM %d: %02x", i, device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
+ printk(BIOS_DEBUG, "\n%02x: ", j);
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
void dump_pci_device(unsigned dev)
{
int i;
- print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for (i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x: %02x", i, val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 327f47d..ed26fad 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -22,12 +22,8 @@
static void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 20) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 15) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 12) & 0x07);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 0x07);
}
static inline void print_pci_devices(void)
@@ -44,7 +40,7 @@ static inline void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -52,20 +48,16 @@ static void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x:", i);
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ printk(BIOS_DEBUG, " %02x", val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -89,34 +81,27 @@ static inline void dump_pci_devices(void)
static inline void dump_spd_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 2; i++) {
unsigned device;
device = DIMM0 + i;
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
@@ -124,30 +109,25 @@ static inline void dump_spd_registers(void)
static inline void dump_smbus_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 1; i < 0x80; i++) {
unsigned device;
device = i;
int j;
- print_debug("smbus: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "smbus: %02x", device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 0ab4d38..39e12d2 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -415,7 +415,7 @@ static void sdram_enable(void)
{
int i;
- print_debug("Ram enable 1\n");
+ printk(BIOS_DEBUG, "Ram enable 1\n");
delay();
delay();
@@ -433,16 +433,16 @@ static void sdram_enable(void)
delay();
delay();
- print_debug("Ram enable 4\n");
+ printk(BIOS_DEBUG, "Ram enable 4\n");
do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE);
delay();
delay();
delay();
- print_debug("Ram enable 5\n");
+ printk(BIOS_DEBUG, "Ram enable 5\n");
do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET);
- print_debug("Ram enable 6\n");
+ printk(BIOS_DEBUG, "Ram enable 6\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
delay();
delay();
@@ -457,7 +457,7 @@ static void sdram_enable(void)
delay();
}
- print_debug("Ram enable 8\n");
+ printk(BIOS_DEBUG, "Ram enable 8\n");
do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL);
/* Set GME-M Mode Select bits back to NORMAL operation mode */
@@ -467,7 +467,7 @@ static void sdram_enable(void)
delay();
delay();
- print_debug("Ram enable 9\n");
+ printk(BIOS_DEBUG, "Ram enable 9\n");
set_initialize_complete();
delay();
@@ -476,11 +476,11 @@ static void sdram_enable(void)
delay();
delay();
- print_debug("After configuration:\n");
+ printk(BIOS_DEBUG, "After configuration:\n");
/* dump_pci_devices(); */
/*
- print_debug("\n\n***** RAM TEST *****\n");
+ printk(BIOS_DEBUG, "\n\n***** RAM TEST *****\n");
ram_check(0, 0xa0000);
ram_check(0x100000, 0x40000000);
*/
@@ -497,7 +497,7 @@ DIMM-independant configuration functions:
static void sdram_set_registers(void)
{
/*
- print_debug("Before configuration:\n");
+ printk(BIOS_DEBUG, "Before configuration:\n");
dump_pci_devices();
*/
}
@@ -572,13 +572,13 @@ static void spd_set_dram_controller_mode(uint8_t dimm_mask)
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate i855 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -965,7 +965,7 @@ static void sdram_set_spd_registers(void)
dimm_mask = spd_get_supported_dimms();
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index e47f762..397bd4b 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -109,12 +109,12 @@ void dump_spd_registers(void)
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 0103c4f..747cbfd 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -25,10 +25,10 @@
#include "cn700.h"
#if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG_MEM(x) print_debug(x)
-#define PRINT_DEBUG_MEM_HEX8(x) print_debug_hex8(x)
-#define PRINT_DEBUG_MEM_HEX16(x) print_debug_hex16(x)
-#define PRINT_DEBUG_MEM_HEX32(x) print_debug_hex32(x)
+#define PRINT_DEBUG_MEM(x) printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_MEM_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_MEM_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_MEM_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG_MEM(x)
diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c
index 4434e57..4826fcf 100644
--- a/src/northbridge/via/cn700/vga.c
+++ b/src/northbridge/via/cn700/vga.c
@@ -84,7 +84,7 @@ static void vga_init(device_t dev)
#undef OLD_BOCHS_METHOD
#ifdef OLD_BOCHS_METHOD
- print_debug("Copying BOCHS BIOS to 0xf000\n");
+ printk(BIOS_DEBUG, "Copying BOCHS BIOS to 0xf000\n");
/*
* Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
* This is for compatibility with the VGA ROM's BIOS callbacks.
diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c
index 7c77bff..39e1753 100644
--- a/src/northbridge/via/cx700/early_smbus.c
+++ b/src/northbridge/via/cx700/early_smbus.c
@@ -46,15 +46,6 @@
#define SMBUS_DELAY() outb(0x80, 0x80)
-/* Debugging macros. */
-#if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
-#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
-#endif
-
/* Internal functions */
#if CONFIG_DEBUG_SMBUS
static void smbus_print_error(unsigned char host_status_register, int loops)
@@ -63,28 +54,26 @@ static void smbus_print_error(unsigned char host_status_register, int loops)
if (host_status_register == 0x00 || host_status_register == 0x40 ||
host_status_register == 0x42)
return;
- print_err("SMBus Error: ");
- print_err_hex8(host_status_register);
+ printk(BIOS_ERR, "SMBus Error: %02x\n", host_status_register);
- print_err("\n");
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\n");
+ printk(BIOS_ERR, "SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\n");
+ printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\n");
+ printk(BIOS_ERR, "Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\n");
+ printk(BIOS_ERR, "Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\n");
+ printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\n");
+ printk(BIOS_ERR, "Host Busy\n");
}
}
#endif
@@ -239,9 +228,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
unsigned int val;
for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
- print_debug("SPD Data for DIMM ");
- print_debug_hex8(dimm);
- print_debug("\n");
+ printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
val = get_spd_data(ctrl, dimm, 0);
if (val == 0xff) {
@@ -249,15 +236,12 @@ static void dump_spd_data(const struct mem_controller *ctrl)
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\n");
+ printk(BIOS_DEBUG, "No DIMM present\n");
regs = 0;
}
for (offset = 0; offset < regs; offset++) {
- print_debug(" Offset ");
- print_debug_hex8(offset);
- print_debug(" = 0x");
- print_debug_hex8(get_spd_data(ctrl, dimm, offset));
- print_debug("\n");
+ printk(BIOS_DEBUG, " Offset %02x = 0x%02x\n",
+ offset, get_spd_data(ctrl, dimm, offset));
}
}
}
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index a2e6dad..32be1ea 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -972,7 +972,7 @@ static void step_20_21(const struct mem_controller *ctrl)
read32(0x102020);
/* Step 21. Normal operation */
- print_spew("RAM Enable 5: Normal operation\n");
+ printk(BIOS_SPEW, "RAM Enable 5: Normal operation\n");
do_ram_command(ctrl, RAM_COMMAND_NORMAL);
udelay(3);
}
@@ -988,58 +988,58 @@ static void step_2_19(const struct mem_controller *ctrl)
pci_write_config8(MEMCTRL, 0x69, val);
/* Step 3 Apply NOP. */
- print_spew("RAM Enable 1: Apply NOP\n");
+ printk(BIOS_SPEW, "RAM Enable 1: Apply NOP\n");
do_ram_command(ctrl, RAM_COMMAND_NOP);
udelay(15);
// Step 4
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
read32(0);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
// Step 5
udelay(400);
/* 6. Precharge all. Wait tRP. */
- print_spew("RAM Enable 2: Precharge all\n");
+ printk(BIOS_SPEW, "RAM Enable 2: Precharge all\n");
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
// Step 7
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
read32(0);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
/* Step 8. Mode register set. */
- print_spew("RAM Enable 4: Mode register set\n");
+ printk(BIOS_SPEW, "RAM Enable 4: Mode register set\n");
do_ram_command(ctrl, RAM_COMMAND_MRS); //enable dll
// Step 9
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
read32(0x102200); //DDR2_ODT_150ohm
else
read32(0x102020);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
// Step 10
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
read32(0x800);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
/* Step 11. Precharge all. Wait tRP. */
- print_spew("RAM Enable 2: Precharge all\n");
+ printk(BIOS_SPEW, "RAM Enable 2: Precharge all\n");
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
// Step 12
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
read32(0x0);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
- print_spew("RAM Enable 3: CBR\n");
+ printk(BIOS_SPEW, "RAM Enable 3: CBR\n");
do_ram_command(ctrl, RAM_COMMAND_CBR);
/* JEDEC says only twice, do 8 times for posterity */
@@ -1047,14 +1047,14 @@ static void step_2_19(const struct mem_controller *ctrl)
for (i = 0; i < 8; i++) {
// Step 14
read32(0);
- print_spew(".");
+ printk(BIOS_SPEW, ".");
// Step 15
udelay(100);
}
/* Step 17. Mode register set. Wait 200us. */
- print_spew("\nRAM Enable 4: Mode register set\n");
+ printk(BIOS_SPEW, "\nRAM Enable 4: Mode register set\n");
//safe value for now, BL=8, WR=4, CAS=4
do_ram_command(ctrl, RAM_COMMAND_MRS);
diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c
index f9b13eb..da2a559 100644
--- a/src/northbridge/via/vx800/early_smbus.c
+++ b/src/northbridge/via/vx800/early_smbus.c
@@ -50,42 +50,38 @@
#define SMBUS_DELAY() outb(0x80, 0x80)
#if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
+#define DEBUG(x...) printk(BIOS_DEBUG, x)
#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
+#define DEBUG(x...) while (0) { }
#endif
/* Internal functions */
static void smbus_print_error(unsigned char host_status_register, int loops)
{
-// print_err("some i2c error\n");
+// printk(BIOS_ERR, "some i2c error\n");
/* Check if there actually was an error */
if (host_status_register == 0x00 || host_status_register == 0x40 ||
host_status_register == 0x42)
return;
- print_err("smbus_error: ");
- print_err_hex8(host_status_register);
- print_err("\n");
+ printk(BIOS_ERR, "smbus_error: %02x\n", host_status_register);
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\n");
+ printk(BIOS_ERR, "SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\n");
+ printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\n");
+ printk(BIOS_ERR, "Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\n");
+ printk(BIOS_ERR, "Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\n");
+ printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\n");
+ printk(BIOS_ERR, "Host Busy\n");
}
}
@@ -185,11 +181,11 @@ void smbus_fixup(const struct mem_controller *mem_ctrl)
ram_slots = ARRAY_SIZE(mem_ctrl->channel0);
if (!ram_slots) {
- print_err("smbus_fixup() thinks there are no RAM slots!\n");
+ printk(BIOS_ERR, "smbus_fixup() thinks there are no RAM slots!\n");
return;
}
- PRINT_DEBUG("Waiting for SMBus to warm up");
+ DEBUG("Waiting for SMBus to warm up");
/*
* Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
@@ -207,13 +203,13 @@ void smbus_fixup(const struct mem_controller *mem_ctrl)
result = get_spd_data(mem_ctrl->channel0[current_slot],
SPD_MEMORY_TYPE);
current_slot++;
- PRINT_DEBUG(".");
+ DEBUG(".");
}
if (i >= SMBUS_TIMEOUT)
- print_err("SMBus timed out while warming up\n");
+ printk(BIOS_ERR, "SMBus timed out while warming up\n");
else
- PRINT_DEBUG("Done\n");
+ DEBUG("Done\n");
}
/* Debugging Function */
@@ -224,9 +220,7 @@ static void dump_spd_data(void)
unsigned int val;
for (dimm = 0; dimm < 8; dimm++) {
- print_debug("SPD Data for DIMM ");
- print_debug_hex8(dimm);
- print_debug("\n");
+ printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
val = get_spd_data(dimm, 0);
if (val == 0xff) {
@@ -234,16 +228,12 @@ static void dump_spd_data(void)
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\n");
+ printk(BIOS_DEBUG, "No DIMM present\n");
regs = 0;
}
- for (offset = 0; offset < regs; offset++) {
- print_debug(" Offset ");
- print_debug_hex8(offset);
- print_debug(" = 0x");
- print_debug_hex8(get_spd_data(dimm, offset));
- print_debug("\n");
- }
+ for (offset = 0; offset < regs; offset++)
+ printk(BIOS_DEBUG, " Offset %02x = 0x%02x\n",
+ offset, get_spd_data(dimm, offset));
}
}
#else
diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c
index 6d58f78..a7a5757 100644
--- a/src/northbridge/via/vx800/raminit.c
+++ b/src/northbridge/via/vx800/raminit.c
@@ -29,10 +29,10 @@
#endif
#if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG_MEM(x) print_debug(x)
-#define PRINT_DEBUG_MEM_HEX8(x) print_debug_hex8(x)
-#define PRINT_DEBUG_MEM_HEX16(x) print_debug_hex16(x)
-#define PRINT_DEBUG_MEM_HEX32(x) print_debug_hex32(x)
+#define PRINT_DEBUG_MEM(x) printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_MEM_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_MEM_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_MEM_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG_MEM(x)
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index b9fed6f..78a1a88 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -296,9 +296,9 @@ static void chrome9hd_biosguide_init_seq(device_t dev)
static void chrome9hd_init(device_t dev)
{
- print_debug("======================================================\n");
- print_debug("== Chrome9 HD INIT\n");
- print_debug("======================================================\n");
+ printk(BIOS_DEBUG, "======================================================\n");
+ printk(BIOS_DEBUG, "== Chrome9 HD INIT\n");
+ printk(BIOS_DEBUG, "======================================================\n");
chrome9hd_biosguide_init_seq(dev);
diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c
index f006ce4..e796d8d 100644
--- a/src/northbridge/via/vx900/early_smbus.c
+++ b/src/northbridge/via/vx900/early_smbus.c
@@ -182,13 +182,13 @@ void dump_spd_data(spd_raw_data spd)
* I originally saw this way to present SPD data in code from VIA. I
* really liked the idea, so here it goes.
*/
- print_debug(" 00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n");
- print_debug("---+------------------------------------------------");
+ printk(BIOS_DEBUG, " 00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n");
+ printk(BIOS_DEBUG, "---+------------------------------------------------");
for (i = 0; i < len; i++) {
reg = spd[i];
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%.2x |", i);
printk(BIOS_DEBUG, " %.2x", reg);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index 2896680..425fe77 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -69,7 +69,7 @@ void vx900_print_strapping_info(void)
{
u8 strap = pci_read_config8(SNMIC, 0x56);
- print_debug("VX900 strapping pins indicate that:\n");
+ printk(BIOS_DEBUG, "VX900 strapping pins indicate that:\n");
printk(BIOS_DEBUG, " ROM is on %s bus\n",
(strap & (1 << 0)) ? "SPI" : "LPC");
printk(BIOS_DEBUG, " Auto reset is %s\n",
@@ -92,13 +92,13 @@ void vx900_print_strapping_info(void)
void vx900_disable_auto_reboot(void)
{
if (pci_read_config8(SNMIC, 0x56) & (1 << 1)) {
- print_debug("Auto-reboot is disabled in hardware\n");
+ printk(BIOS_DEBUG, "Auto-reboot is disabled in hardware\n");
return;
}
/* Disable the GP3 timer, which is the root of all evil */
pci_write_config8(LPC, 0x98, 0);
/* Yep, that's all it takes */
- print_debug("GP3 timer disabled."
+ printk(BIOS_DEBUG, "GP3 timer disabled."
" Auto-reboot should not give you any more trouble.\n");
}
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index ac5e4c8..bb2f1b2 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -146,7 +146,7 @@ static void vx900_lpc_ioapic_setup(device_t dev)
return;
}
- print_debug("VX900 LPC: Setting up the south module IOAPIC.\n");
+ printk(BIOS_DEBUG, "VX900 LPC: Setting up the south module IOAPIC.\n");
/* Enable IOAPIC
* So much work for one line of code. Talk about bloat :)
* The 8259 PIC should still work even if the IOAPIC is enabled, so
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index f9c225d..e1f744c 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -80,7 +80,7 @@ static u64 vx900_get_top_of_ram(device_t mcu)
static void killme_debug_4g_remap_reg(u32 reg32)
{
if (reg32 & (1 << 0))
- print_debug("Mem remapping enabled\n");
+ printk(BIOS_DEBUG, "Mem remapping enabled\n");
u64 remapstart = (reg32 >> 2) & 0x3ff;
u64 remapend = (reg32 >> 14) & 0x3ff;
remapstart <<= 26;
@@ -122,7 +122,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
* becomes accessible at "to" to "until"
*/
if (tolm >= vx900_get_top_of_ram(mcu)) {
- print_debug("Nothing to remap\n");
+ printk(BIOS_DEBUG, "Nothing to remap\n");
}
/* This is how the Vendor BIOS. Keep it for comparison for now */
@@ -220,11 +220,11 @@ static void vx900_set_resources(device_t dev)
{
u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
- print_debug("========================================"
+ printk(BIOS_DEBUG, "========================================"
"========================================\n");
- print_debug("============= VX900 memory sizing & Co. "
+ printk(BIOS_DEBUG, "============= VX900 memory sizing & Co. "
"========================================\n");
- print_debug("========================================"
+ printk(BIOS_DEBUG, "========================================"
"========================================\n");
int idx = 10;
@@ -282,7 +282,7 @@ static void vx900_set_resources(device_t dev)
set_top_of_ram(tolmk << 10);
- print_debug("======================================================\n");
+ printk(BIOS_DEBUG, "======================================================\n");
assign_resources(dev->link_list);
}
diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c
index 109e5c9..b748c39 100644
--- a/src/northbridge/via/vx900/pcie.c
+++ b/src/northbridge/via/vx900/pcie.c
@@ -72,11 +72,11 @@ static void vx900_pcie_link_init(device_t dev)
pci_write_config8(dev, 0xa4, 0xff);
if (pci_read_config8(dev, 0x4a) & (1 << 3))
- print_debug("Unsupported request detected.\n");
+ printk(BIOS_DEBUG, "Unsupported request detected.\n");
pci_write_config8(dev, 0x15a, 0xff);
if (pci_read_config8(dev, 0x15a) & (1 << 1))
- print_debug("Negotiation pending.\n");
+ printk(BIOS_DEBUG, "Negotiation pending.\n");
/* Step 4: Read vendor ID */
/* FIXME: Do we want to run through the whole sequence and delay boot
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index e6dace3..d1b2beb 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -1512,7 +1512,7 @@ static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks)
/* vvvvvvvvvv FIXME: Fix odd rank init vvvvvvvvvv */
if ((i & 1)) {
printk(BIOS_EMERG, "I cannot initialize rank %zu\n", i);
- print_emerg("I have to disable it\n");
+ printk(BIOS_EMERG, "I have to disable it\n");
continue;
}
/* ^^^^^^^^^^ FIXME: Fix odd rank init ^^^^^^^^^^ */
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index 63295e5..c5f36a8 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -44,47 +44,47 @@ static void vx900_print_sata_errors(u32 flags)
(flags & (1 << 27)) ? "detected" : "not detected");
/* Errors */
if (flags & (1 << 0))
- print_debug("\tRecovered data integrity ERROR\n");
+ printk(BIOS_DEBUG, "\tRecovered data integrity ERROR\n");
if (flags & (1 << 1))
- print_debug("\tRecovered data communication ERROR\n");
+ printk(BIOS_DEBUG, "\tRecovered data communication ERROR\n");
if (flags & (1 << 8))
- print_debug("\tNon-recovered Transient Data Integrity ERROR\n");
+ printk(BIOS_DEBUG, "\tNon-recovered Transient Data Integrity ERROR\n");
if (flags & (1 << 9))
- print_debug("\tNon-recovered Persistent Communication or"
+ printk(BIOS_DEBUG, "\tNon-recovered Persistent Communication or"
"\tData Integrity ERROR\n");
if (flags & (1 << 10))
- print_debug("\tProtocol ERROR\n");
+ printk(BIOS_DEBUG, "\tProtocol ERROR\n");
if (flags & (1 << 11))
- print_debug("\tInternal ERROR\n");
+ printk(BIOS_DEBUG, "\tInternal ERROR\n");
if (flags & (1 << 17))
- print_debug("\tPHY Internal ERROR\n");
+ printk(BIOS_DEBUG, "\tPHY Internal ERROR\n");
if (flags & (1 << 19))
- print_debug("\t10B to 8B Decode ERROR\n");
+ printk(BIOS_DEBUG, "\t10B to 8B Decode ERROR\n");
if (flags & (1 << 20))
- print_debug("\tDisparity ERROR\n");
+ printk(BIOS_DEBUG, "\tDisparity ERROR\n");
if (flags & (1 << 21))
- print_debug("\tCRC ERROR\n");
+ printk(BIOS_DEBUG, "\tCRC ERROR\n");
if (flags & (1 << 22))
- print_debug("\tHandshake ERROR\n");
+ printk(BIOS_DEBUG, "\tHandshake ERROR\n");
if (flags & (1 << 23))
- print_debug("\tLink Sequence ERROR\n");
+ printk(BIOS_DEBUG, "\tLink Sequence ERROR\n");
if (flags & (1 << 24))
- print_debug("\tTransport State Transition ERROR\n");
+ printk(BIOS_DEBUG, "\tTransport State Transition ERROR\n");
if (flags & (1 << 25))
- print_debug("\tUNRECOGNIZED FIS type\n");
+ printk(BIOS_DEBUG, "\tUNRECOGNIZED FIS type\n");
}
static void vx900_dbg_sata_errors(device_t dev)
{
/* Port 0 */
if (pci_read_config8(dev, 0xa0) & (1 << 0)) {
- print_debug("Device detected in SATA port 0.\n");
+ printk(BIOS_DEBUG, "Device detected in SATA port 0.\n");
u32 flags = pci_read_config32(dev, 0xa8);
vx900_print_sata_errors(flags);
};
/* Port 1 */
if (pci_read_config8(dev, 0xa1) & (1 << 0)) {
- print_debug("Device detected in SATA port 1.\n");
+ printk(BIOS_DEBUG, "Device detected in SATA port 1.\n");
u32 flags = pci_read_config32(dev, 0xac);
vx900_print_sata_errors(flags);
};
@@ -147,21 +147,18 @@ static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg)
static void vx900_sata_dump_phy_config(sata_phy_config cfg)
{
- print_debug("SATA PHY config:\n");
+ printk(BIOS_DEBUG, "SATA PHY config:\n");
int i;
for (i = 0; i < sizeof(sata_phy_config); i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x:", i);
val = cfg[i];
if ((i & 7) == 0)
- print_debug(" |");
- print_debug_char(' ');
- print_debug_hex8(val);
+ printk(BIOS_DEBUG, " |");
+ printk(BIOS_DEBUG, " %02x", val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
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