[coreboot-gerrit] New patch to review for coreboot: b7c44ba cpu/amd/model_10xxx/*: Trivial - Fix indent style
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Mon Jan 5 18:07:34 CET 2015
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8105
-gerrit
commit b7c44bae0fcb0dc534bf9e6c52d85ec2064a8ae2
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Tue Jan 6 04:06:44 2015 +1100
cpu/amd/model_10xxx/*: Trivial - Fix indent style
Change-Id: I54df9ed04a5100fe514d15bf82d0b58a3d9668f7
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/cpu/amd/model_10xxx/fidvid.c | 512 ++++++++++++++---------------
src/cpu/amd/model_10xxx/model_10xxx_init.c | 1 -
2 files changed, 249 insertions(+), 264 deletions(-)
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index d3c67a9..8f34ffe 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -146,121 +146,121 @@ static void enable_fid_change(u8 fid)
dword |= (u32) fid & 0x1F;
dword |= 1 << 5; // enable
pci_write_config32(dev, 0xd4, dword);
- printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
- dword);
+ printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword);
}
}
static void applyBoostFIDOffset( device_t dev ) {
- // BKDG 2.4.2.8
- // revision E only, but E is apparently not supported yet, therefore untested
- if ((cpuid_edx(0x80000007) & CPB_MASK)
- && ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) {
- u32 core = get_node_core_id_x().coreid;
- u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
- msr_t msr = rdmsr(PS_REG_BASE);
- u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
- cpuFid = cpuFid + asymetricBoostThisCore;
- msr.lo &= ~PS_CPU_FID_MASK;
- msr.lo |= cpuFid ;
- wrmsr(PS_REG_BASE , msr);
-
- }
+ // BKDG 2.4.2.8
+ // revision E only, but E is apparently not supported yet, therefore untested
+ if ((cpuid_edx(0x80000007) & CPB_MASK) && ((cpuid_ecx(0x80000008) & NC_MASK) == 5)) {
+ u32 core = get_node_core_id_x().coreid;
+ u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
+ msr_t msr = rdmsr(PS_REG_BASE);
+ u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
+ cpuFid = cpuFid + asymetricBoostThisCore;
+ msr.lo &= ~PS_CPU_FID_MASK;
+ msr.lo |= cpuFid ;
+ wrmsr(PS_REG_BASE , msr);
+ }
}
-static void enableNbPState1( device_t dev ) {
- u32 cpuRev = mctGetLogicalCPUID(0xFF);
- if (cpuRev & AMD_FAM10_C3) {
- u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
- if ( nbPState){
- u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
- u32 i;
- for (i = nbPState; i < NM_PS_REG; i++) {
- msr_t msr = rdmsr(PS_REG_BASE + i);
- if (msr.hi & PS_EN_MASK ) {
- msr.hi |= NB_DID_M_ON;
- msr.lo &= NB_VID_MASK_OFF;
- msr.lo |= ( nbVid1 << NB_VID_POS);
- wrmsr(PS_REG_BASE + i, msr);
- }
- }
- }
- }
+static void enableNbPState1(device_t dev) {
+ u32 cpuRev = mctGetLogicalCPUID(0xFF);
+ if (cpuRev & AMD_FAM10_C3) {
+ u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
+ if (nbPState) {
+ u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
+ u32 i;
+ for (i = nbPState; i < NM_PS_REG; i++) {
+ msr_t msr = rdmsr(PS_REG_BASE + i);
+ if (msr.hi & PS_EN_MASK ) {
+ msr.hi |= NB_DID_M_ON;
+ msr.lo &= NB_VID_MASK_OFF;
+ msr.lo |= ( nbVid1 << NB_VID_POS);
+ wrmsr(PS_REG_BASE + i, msr);
+ }
+ }
+ }
+ }
}
-static u8 setPStateMaxVal( device_t dev ) {
- u8 i,maxpstate=0;
- for (i = 0; i < NM_PS_REG; i++) {
- msr_t msr = rdmsr(PS_REG_BASE + i);
- if (msr.hi & PS_IDD_VALUE_MASK) {
- msr.hi |= PS_EN_MASK ;
- wrmsr(PS_REG_BASE + i, msr);
- }
- if (msr.hi & PS_EN_MASK) {
- maxpstate = i;
- }
- }
- //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
- u32 reg = pci_read_config32(dev, CPTC2);
- reg &= PS_MAX_VAL_MASK;
- reg |= (maxpstate << PS_MAX_VAL_POS);
- pci_write_config32(dev, CPTC2,reg);
- return maxpstate;
+static u8 setPStateMaxVal(device_t dev) {
+ u8 i, maxpstate = 0;
+
+ for (i = 0; i < NM_PS_REG; i++) {
+ msr_t msr = rdmsr(PS_REG_BASE + i);
+ if (msr.hi & PS_IDD_VALUE_MASK) {
+ msr.hi |= PS_EN_MASK ;
+ wrmsr(PS_REG_BASE + i, msr);
+ }
+ if (msr.hi & PS_EN_MASK) {
+ maxpstate = i;
+ }
+ }
+
+ //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
+ u32 reg = pci_read_config32(dev, CPTC2);
+ reg &= PS_MAX_VAL_MASK;
+ reg |= (maxpstate << PS_MAX_VAL_POS);
+ pci_write_config32(dev, CPTC2,reg);
+
+ return maxpstate;
}
-static void dualPlaneOnly( device_t dev ) {
- // BKDG 2.4.2.7
-
- u32 cpuRev = mctGetLogicalCPUID(0xFF);
- if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2)
- && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E
- if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK)
- && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){
- if (cpuid_edx(0x80000007) & CPB_MASK) {
- // revision E only, but E is apparently not supported yet, therefore untested
- msr_t minPstate = rdmsr(0xC0010065);
- wrmsr(0xC0010065, rdmsr(0xC0010068) );
- wrmsr(0xC0010068,minPstate);
- } else {
- msr_t msr;
- msr.lo=0; msr.hi=0;
- wrmsr(0xC0010064, rdmsr(0xC0010068) );
- wrmsr(0xC0010068, msr );
- }
-
- //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
- u8 maxpstate = setPStateMaxVal(dev);
-
- u32 reg = pci_read_config32(dev, HTC_REG);
- reg &= HTC_PS_LMT_MASK;
- reg |= (maxpstate << PS_LIMIT_POS);
- pci_write_config32(dev, HTC_REG,reg);
-
- }
- }
+static void dualPlaneOnly(device_t dev) {
+// BKDG 2.4.2.7
+ u32 cpuRev = mctGetLogicalCPUID(0xFF);
+
+ // should be rev C or rev E but there's no constant for E
+ if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) && (cpuRev & AMD_DR_Cx)) {
+ if ((pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) && (pci_read_config32(dev, 0xA0) & PVI_MODE)) {
+ if (cpuid_edx(0x80000007) & CPB_MASK) {
+ // revision E only, but E is apparently not supported yet, therefore untested
+ msr_t minPstate = rdmsr(0xC0010065);
+ wrmsr(0xC0010065, rdmsr(0xC0010068));
+ wrmsr(0xC0010068,minPstate);
+ } else {
+ msr_t msr;
+ msr.lo=0;
+ msr.hi=0;
+ wrmsr(0xC0010064, rdmsr(0xC0010068));
+ wrmsr(0xC0010068, msr );
+ }
+
+ //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
+ u8 maxpstate = setPStateMaxVal(dev);
+
+ u32 reg = pci_read_config32(dev, HTC_REG);
+ reg &= HTC_PS_LMT_MASK;
+ reg |= (maxpstate << PS_LIMIT_POS);
+ pci_write_config32(dev, HTC_REG,reg);
+ }
+ }
}
static int vidTo100uV(u8 vid)
-{// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV
- // BKDG #31116 rev 3.48 2.4.1.6
- int voltage;
- if (vid >= 0x7c) {
- voltage = 0;
- } else {
- voltage = (15500 - (125*vid));
- }
- return voltage;
+{
+ // returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV
+ // BKDG #31116 rev 3.48 2.4.1.6
+ int voltage;
+ if (vid >= 0x7c) {
+ voltage = 0;
+ } else {
+ voltage = (15500 - (125*vid));
+ }
+ return voltage;
}
static void setVSRamp(device_t dev) {
/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime]
- * If this field accepts 8 values between 10 and 500 us why
- * does page 324 say "BIOS should set this field to 001b."
- * (20 us) ?
- * Shouldn't it depend on the voltage regulators, mainboard
- * or something ?
- */
- u32 dword;
+ * If this field accepts 8 values between 10 and 500 us why
+ * does page 324 say "BIOS should set this field to 001b."
+ * (20 us) ?
+ * Shouldn't it depend on the voltage regulators, mainboard
+ * or something ?
+ */
+ u32 dword;
dword = pci_read_config32(dev, 0xd8);
dword &= VSRAMP_MASK;
dword |= VSRAMP_VALUE;
@@ -278,12 +278,12 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
/* This function calculates the VsSlamTime using the range of possible
* voltages instead of a hardcoded 200us.
- * Note: his function is called only from prep_fid_change,
- * and that from init_cpus.c finalize_node_setup()
- * (after set AMD MSRs and init ht )
+ * Note: his function is called only from prep_fid_change,
+ * and that from init_cpus.c finalize_node_setup()
+ * (after set AMD MSRs and init ht )
*/
- /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
+ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
/* Calculate Slam Time
* Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV
* In our case, we will scale the values by 100 to avoid
@@ -299,16 +299,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
pviModeFlag = 0;
/* Get P0's voltage */
- /* MSRC001_00[68:64] are not programmed yet when called from
- prep_fid_change, one might use F4x1[F0:E0] instead, but
- theoretically MSRC001_00[68:64] are equal to them after
- reset. */
+ /* MSRC001_00[68:64] are not programmed yet when called from
+ * prep_fid_change, one might use F4x1[F0:E0] instead, but
+ * theoretically MSRC001_00[68:64] are equal to them after
+ * reset.
+ */
msr = rdmsr(0xC0010064);
highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
- if (!(msr.hi & 0x80000000)) {
- printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");
- highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0)
- >> PS_CPU_VID_SHFT) & 0x7F);
+ if (!(msr.hi & 0x80000000)) {
+ printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");
+ highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) >> PS_CPU_VID_SHFT) & 0x7F);
}
/* If SVI, we only care about CPU VID.
@@ -336,7 +336,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
/* If SVI, we only care about CPU VID.
* If PVI, determine the higher voltage b/t NB and CPU
* BKDG 2.4.1.7 (a)
- */
+ */
if (pviModeFlag) {
bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
if (lowVoltageVid > bValue)
@@ -351,7 +351,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
if (lowVoltageVid < bValue)
lowVoltageVid = bValue;
- u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB;
+ u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB;
minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */
@@ -372,23 +372,23 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
}
static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
- u8 link0isGen3 = 0;
- u8 offset;
- if (AMD_CpuFindCapability(node, 0, &offset)) {
- link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 );
+ u8 link0isGen3 = 0;
+ u8 offset;
+
+ if (AMD_CpuFindCapability(node, 0, &offset)) {
+ link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 );
+ }
+ /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
+ * S1g3 in link Gen3 mode, but I don't know how to tell
+ * package S1g3 from S1g4
+ */
+ if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) && link0isGen3) {
+ return 5 ; /* divide clk by 128*/
+ } else {
+ return 4 ; /* divide clk by 16 */
}
- /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
- S1g3 in link Gen3 mode, but I don't know how to tell
- package S1g3 from S1g4 */
- if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
- && link0isGen3) {
- return 5 ; /* divide clk by 128*/
- } else {
- return 4 ; /* divide clk by 16 */
- }
}
-
static u32 power_up_down(int node, u8 procPkg) {
u32 dword=0;
/* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */
@@ -504,83 +504,79 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
/* Note the following settings are additional from the ported
* function setFidVidRegs()
*/
- /* adjust FIFO between nb and core clocks to max allowed
- values (min latency) */
+ /* adjust FIFO between nb and core clocks to max allowed values (min latency) */
u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK;
- u8 nbSynPtrAdj;
- if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) )
- || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) {
- nbSynPtrAdj = 5;
+ u8 nbSynPtrAdj;
+
+ if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx)) || ((cpuRev & AMD_RB_C3) && (nbPstate!=0))) {
+ nbSynPtrAdj = 5;
} else {
- nbSynPtrAdj = 6;
+ nbSynPtrAdj = 6;
}
u32 dword = pci_read_config32(dev, 0xDc);
- dword &= ~ NB_SYN_PTR_ADJ_MASK;
+ dword &= ~ NB_SYN_PTR_ADJ_MASK;
dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS;
- /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */
+ /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */
pci_write_config32(dev, 0xdc, dword);
}
static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
- /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */
- u32 dword;
- u32 c1= 1;
- if (cpuRev & (AMD_DR_Bx)) {
- // will coreboot ever enable cache scrubbing ?
- // if it does, will it be enough to check the current state
- // or should we configure for what we'll set up later ?
- dword = pci_read_config32(dev, 0x58);
- u32 scrubbingCache = dword &
- ( (0x1F << 16) // DCacheScrub
- | (0x1F << 8) ); // L2Scrub
- if (scrubbingCache) {
- c1 = 0x80;
- } else {
- c1 = 0xA0;
- }
+ /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */
+ u32 dword;
+ u32 c1 = 1;
+ if (cpuRev & (AMD_DR_Bx)) {
+ // will coreboot ever enable cache scrubbing ?
+ // if it does, will it be enough to check the current state
+ // or should we configure for what we'll set up later ?
+ dword = pci_read_config32(dev, 0x58);
+ u32 scrubbingCache = dword & ((0x1F << 16) /* DCacheScrub */ | (0x1F << 8)); /* L2Scrub */
+ if (scrubbingCache) {
+ c1 = 0x80;
+ } else {
+ c1 = 0xA0;
+ }
} else { // rev C or later
- // same doubt as cache scrubbing: ok to check current state ?
- dword = pci_read_config32(dev, 0xDC);
- u32 cacheFlushOnHalt = dword & (7 << 16);
- if (!cacheFlushOnHalt) {
- c1 = 0x80;
- }
- }
- dword = (c1 << 24) | (0xE641E6);
+ // same doubt as cache scrubbing: ok to check current state ?
+ dword = pci_read_config32(dev, 0xDC);
+ u32 cacheFlushOnHalt = dword & (7 << 16);
+ if (!cacheFlushOnHalt) {
+ c1 = 0x80;
+ }
+ }
+ dword = (c1 << 24) | (0xE641E6);
pci_write_config32(dev, 0x84, dword);
- /* FIXME: BKDG Table 100 says if the link is at a Gen1
-frequency and the chipset does not support a 10us minimum LDTSTOP
-assertion time, then { If ASB2 && SVI then smaf001 = F6h else
-smaf001=87h. } else ... I hardly know what it means or how to check
-it from here, so I bluntly assume it is false and code here the else,
-which is easier */
-
- u32 smaf001 = 0xE6;
- if (cpuRev & AMD_DR_Bx ) {
- smaf001 = 0xA6;
- } else {
- #if CONFIG_SVI_HIGH_FREQ
- if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
- smaf001 = 0xF6;
+/* FIXME: BKDG Table 100 says if the link is at a Gen1
+ * frequency and the chipset does not support a 10us minimum LDTSTOP
+ * assertion time, then { If ASB2 && SVI then smaf001 = F6h else
+ * smaf001=87h. } else ... I hardly know what it means or how to check
+ * it from here, so I bluntly assume it is false and code here the else,
+ * which is easier
+ */
+
+ u32 smaf001 = 0xE6;
+ if (cpuRev & AMD_DR_Bx ) {
+ smaf001 = 0xA6;
+ } else {
+#if CONFIG_SVI_HIGH_FREQ
+ if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
+ smaf001 = 0xF6;
}
- #endif
- }
- u32 fidvidChange = 0;
- if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX))
- || (cpuRev & AMD_RB_C3) ) {
- fidvidChange=0x0B;
- }
- dword = (0xE6 << 24) | (fidvidChange << 16)
- | (smaf001 << 8) | 0x81;
+#endif
+ }
+ u32 fidvidChange = 0;
+ if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) || (cpuRev & AMD_RB_C3) ) {
+ fidvidChange = 0x0B;
+ }
+ dword = (0xE6 << 24) | (fidvidChange << 16) | (smaf001 << 8) | 0x81;
pci_write_config32(dev, 0x80, dword);
}
static void prep_fid_change(void)
{
- u32 dword;
+ u32 dword;
u32 nodes;
device_t dev;
int i;
@@ -592,20 +588,20 @@ static void prep_fid_change(void)
for (i = 0; i < nodes; i++) {
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
dev = NODE_PCI(i, 3);
- u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
- u8 procPkg = mctGetProcessorPackageType();
+ u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
+ u8 procPkg = mctGetProcessorPackageType();
setVSRamp(dev);
/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
/* Figure out the value for VsSlamTime and program it */
recalculateVsSlamTimeSettingOnCorePre(dev);
- config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
+ config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
- config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
+ config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
config_nb_syn_ptr_adj(dev,cpuRev);
- config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
+ config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
dword = pci_read_config32(dev, 0x80);
printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
@@ -617,54 +613,51 @@ static void prep_fid_change(void)
printk(BIOS_DEBUG, " F3xD8: %08x \n", dword);
dword = pci_read_config32(dev, 0xDC);
printk(BIOS_DEBUG, " F3xDC: %08x \n", dword);
-
-
}
}
static void waitCurrentPstate(u32 target_pstate){
- msr_t initial_msr = rdmsr(TSC_MSR);
- msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
- msr_t tsc_msr;
- u8 timedout ;
-
- /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
- * P1 that is a copy of P0, therefore has the same NB DID but the
- * TSC will count twice per tick, so we have to wait for twice the
- * count to achieve the desired timeout. But I'm likely to
- * misunderstand this...
- */
- u32 corrected_timeout = ( (pstate_msr.lo==1)
- && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
- WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ;
- msr_t timeout;
-
- timeout.lo = initial_msr.lo + corrected_timeout ;
- timeout.hi = initial_msr.hi;
- if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
- timeout.hi++;
- }
-
- // assuming TSC ticks at 1.25 ns per tick (800 MHz)
- do {
- pstate_msr = rdmsr(CUR_PSTATE_MSR);
- tsc_msr = rdmsr(TSC_MSR);
- timedout = (tsc_msr.hi > timeout.hi)
- || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
- } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
-
- if (pstate_msr.lo != target_pstate) {
- msr_t limit_msr = rdmsr(0xc0010061);
- printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo);
-
- do { // should we just go on instead ?
- pstate_msr = rdmsr(CUR_PSTATE_MSR);
- } while ( pstate_msr.lo != target_pstate ) ;
- }
+ msr_t initial_msr = rdmsr(TSC_MSR);
+ msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
+ msr_t tsc_msr;
+ msr_t timeout;
+ u8 timedout;
+
+ /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
+ * P1 that is a copy of P0, therefore has the same NB DID but the
+ * TSC will count twice per tick, so we have to wait for twice the
+ * count to achieve the desired timeout. But I'm likely to
+ * misunderstand this...
+ */
+ u32 corrected_timeout = ((pstate_msr.lo==1)
+ && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT;
+
+ timeout.lo = initial_msr.lo + corrected_timeout ;
+ timeout.hi = initial_msr.hi;
+ if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
+ timeout.hi++;
+ }
+
+ // assuming TSC ticks at 1.25 ns per tick (800 MHz)
+ do {
+ pstate_msr = rdmsr(CUR_PSTATE_MSR);
+ tsc_msr = rdmsr(TSC_MSR);
+ timedout = (tsc_msr.hi > timeout.hi) || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo));
+ } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
+
+ if (pstate_msr.lo != target_pstate) {
+ msr_t limit_msr = rdmsr(0xc0010061);
+ printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo);
+
+ do { // should we just go on instead ?
+ pstate_msr = rdmsr(CUR_PSTATE_MSR);
+ } while ( pstate_msr.lo != target_pstate ) ;
+ }
}
-static void set_pstate(u32 nonBoostedPState) {
- msr_t msr;
+static void set_pstate(u32 nonBoostedPState)
+{
+ msr_t msr;
// Transition P0 for calling core.
msr = rdmsr(0xC0010062);
@@ -673,12 +666,9 @@ static void set_pstate(u32 nonBoostedPState) {
wrmsr(0xC0010062, msr);
/* Wait for P0 to set. */
- waitCurrentPstate(nonBoostedPState);
+ waitCurrentPstate(nonBoostedPState);
}
-
-
-
static void UpdateSinglePlaneNbVid(void)
{
u32 nbVid, cpuVid;
@@ -704,23 +694,23 @@ static void UpdateSinglePlaneNbVid(void)
}
static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
- {
- msr_t msr;
- u8 startup_pstate;
+{
+ msr_t msr;
+ u8 startup_pstate;
- /* This function sets NbVid before the warm reset.
- * Get StartupPstate from MSRC001_0071.
+ /* This function sets NbVid before the warm reset.
+ * Get StartupPstate from MSRC001_0071.
* Read Pstate register pointed by [StartupPstate].
- * and copy its content to P0 and P1 registers.
- * Copy newNbVid to P0[NbVid].
- * transition to P1 on all cores,
- * then transition to P0 on core 0.
- * Wait for MSRC001_0063[CurPstate] = 000b on core 0.
- * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration
- * for SVI and Single-Plane PVI Systems
- */
-
- msr = rdmsr(0xc0010071);
+ * and copy its content to P0 and P1 registers.
+ * Copy newNbVid to P0[NbVid].
+ * transition to P1 on all cores,
+ * then transition to P0 on core 0.
+ * Wait for MSRC001_0063[CurPstate] = 000b on core 0.
+ * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration
+ * for SVI and Single-Plane PVI Systems
+ */
+
+ msr = rdmsr(0xc0010071);
startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
/* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for
@@ -731,13 +721,13 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
wrmsr(0xC0010065, msr);
wrmsr(0xC0010064, msr);
- /* missing step 2 from BDKG , F3xDC[PstateMaxVal] =
- * max(1,F3xDC[PstateMaxVal] ) because it would take
- * synchronization between cores and we don't think
- * PstatMaxVal is going to be 0 on cold reset anyway ?
+ /* missing step 2 from BDKG , F3xDC[PstateMaxVal] =
+ * max(1,F3xDC[PstateMaxVal] ) because it would take
+ * synchronization between cores and we don't think
+ * PstatMaxVal is going to be 0 on cold reset anyway ?
*/
- if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) {
- printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
+ if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) {
+ printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
};
msr.lo &= ~0xFE000000; // clear nbvid
@@ -753,12 +743,11 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
if (coreid == 0) {
set_pstate(0);
- }
+ }
/* missing step 7 (restore PstateMax to 0 if needed) because
* we skipped step 2
*/
-
}
static u32 needs_NB_COF_VID_update(void)
@@ -888,7 +877,6 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
-
}
static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
@@ -930,7 +918,6 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
/* Set and wait for StartupPstate to set. */
set_pstate(StartupPstate);
-
}
static void finalPstateChange(void)
@@ -979,9 +966,9 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid)
dtemp |= PLLLOCK_DFT_L;
pci_write_config32(dev, 0xA0, dtemp);
- dualPlaneOnly(dev);
- applyBoostFIDOffset(dev);
- enableNbPState1(dev);
+ dualPlaneOnly(dev);
+ applyBoostFIDOffset(dev);
+ enableNbPState1(dev);
finalPstateChange();
@@ -1002,7 +989,6 @@ struct ap_apicid_st {
static void store_ap_apicid(unsigned ap_apicid, void *gp)
{
struct ap_apicid_st *p = gp;
-
p->apicid[p->num++] = ap_apicid;
}
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index c6cf64a..453684a 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -113,7 +113,6 @@ static void model_10xxx_init(device_t dev)
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
-
}
static struct device_operations cpu_dev_ops = {
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