[coreboot-gerrit] Patch set updated for coreboot: 6e9b068 ipq8064: add SOC initialization skeleton

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8000

-gerrit

commit 6e9b0684f6e3745e3a16c1678e1aaa1f75da9610
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue May 13 17:47:57 2014 -0700

    ipq8064: add SOC initialization skeleton
    
    The main benefit of adding this skeleton is the addition of the
    correct memory map to CBMEM. Attempts to load depthcharge do not fail
    because of unavailability of the bounce buffer.
    
    BUG=chrome-os-partner:27784
    TEST=boot updated firmware on AP148, observe
    
       CPU: Qualcomm 8064
    
      in the ramstage console output as well as not failing to load
      depthcharge any more.
    
    Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/199675
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013
---
 src/soc/qualcomm/ipq806x/Makefile.inc |  1 +
 src/soc/qualcomm/ipq806x/soc.c        | 49 +++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 91cdd93..f6acbed 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -34,6 +34,7 @@ romstage-y += cbmem.c
 ramstage-y += cbmem.c
 ramstage-y += clock.c
 ramstage-y += gpio.c
+ramstage-y += soc.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 ramstage-y += timer.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c
diff --git a/src/soc/qualcomm/ipq806x/soc.c b/src/soc/qualcomm/ipq806x/soc.c
new file mode 100644
index 0000000..53f5716
--- /dev/null
+++ b/src/soc/qualcomm/ipq806x/soc.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void soc_read_resources(device_t dev)
+{
+	ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB,
+		     CONFIG_DRAM_SIZE_MB * (1 << 10));
+}
+
+static void soc_init(device_t dev)
+{
+	printk(BIOS_INFO, "CPU: Qualcomm 8064\n");
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.init		= soc_init,
+};
+
+static void enable_soc_dev(device_t dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_qualcomm_ipq806x_ops = {
+	CHIP_NAME("SOC Qualcomm 8064")
+	.enable_dev = enable_soc_dev,
+};