[coreboot-gerrit] New patch to review for coreboot: eac3413 samus: Minor fixes for P1.9 boards

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8048

-gerrit

commit eac3413f0cff28f25ec4550c08b800515a26981d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jun 10 10:05:03 2014 -0700

    samus: Minor fixes for P1.9 boards
    
    - Put SSD into reset on transition to S3/S5 to prevent leakage
    - Fix GPIO number for wlan disable used in smihandler
    - Enable generic hub driver in libpayload
    - Fix comment in devicetree about S0ix
    
    BUG=chrome-os-partner:28502
    BRANCH=None
    TEST=Build and boot on samus
    
    Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/203185
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0
---
 src/mainboard/google/samus/devicetree.cb | 2 +-
 src/mainboard/google/samus/smihandler.c  | 8 ++++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index ce13a1d..95ab44b 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -52,7 +52,7 @@ chip soc/intel/broadwell
 	# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
 	register "icc_clock_disable" = "0x013b0000"
 
-	# Enable S0ix
+	# Disable S0ix for now
 	register "s0ix_enable" = "0"
 
 	device cpu_cluster 0 on
diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c
index b43b46a..932d606 100644
--- a/src/mainboard/google/samus/smihandler.c
+++ b/src/mainboard/google/samus/smihandler.c
@@ -32,8 +32,8 @@
 #include <broadwell/smm.h>
 #include "ec.h"
 
-/* GPIO46 controls the WLAN_DISABLE_L signal. */
-#define GPIO_WLAN_DISABLE_L 46
+#define GPIO_SSD_RESET_L    47
+#define GPIO_WLAN_DISABLE_L 42
 #define GPIO_LTE_DISABLE_L  59
 
 int mainboard_io_trap_handler(int smif)
@@ -103,6 +103,8 @@ void mainboard_smi_sleep(u8 slp_typ)
 				1, USB_CHARGE_MODE_DISABLED);
 		}
 
+		/* Put SSD in reset to prevent leak. */
+		set_gpio(GPIO_SSD_RESET_L, 0);
 		/* Prevent leak from standby rail to WLAN rail in S3. */
 		set_gpio(GPIO_WLAN_DISABLE_L, 0);
 		/* Disable LTE */
@@ -119,6 +121,8 @@ void mainboard_smi_sleep(u8 slp_typ)
 				1, USB_CHARGE_MODE_DISABLED);
 		}
 
+		/* Put SSD in reset to prevent leak. */
+		set_gpio(GPIO_SSD_RESET_L, 0);
 		/* Prevent leak from standby rail to WLAN rail in S5. */
 		set_gpio(GPIO_WLAN_DISABLE_L, 0);
 		/* Disable LTE */