[coreboot-gerrit] New patch to review for coreboot: b4f1ed9 arm: lpae: Set XN and PXN bits for noncacheable regions
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Sat Jan 3 00:06:41 CET 2015
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8043
-gerrit
commit b4f1ed92af6d17805d45296aec704f396f5eeaf5
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date: Fri Jun 6 17:00:10 2014 -0700
arm: lpae: Set XN and PXN bits for noncacheable regions
Add XN/PXN bits to prevent cpu from fetching speculative instructions
on noncacheable region.
BUG=chrome-os-partner:28568
BRANCH=nyan
TEST=Build and run reboot tests on nyan_big
Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
Original-Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b
Original-Reviewed-on: https://chromium-review.googlesource.com/203447
Original-Tested-by: Jimmy Zhang <jimmzhang at nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang at nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
(cherry picked from commit c3d585bdfcbe9330e5c6f51d1fcf45aec9f26755)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: Icf552e2f1ba20255915b24b4f96a179a2e7d08fe
---
src/arch/arm/armv7/mmu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 1b5957c..bd12946 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -42,7 +42,7 @@
/* See B3.6.2 of ARMv7 Architecture Reference Manual */
/* TODO: Utilize the contiguous hint flag */
#define ATTR_BASE (\
- 0ULL << 54 | /* PN. 0:Not restricted */ \
+ 0ULL << 54 | /* XN. 0:Not restricted */ \
0ULL << 53 | /* PXN. 0:Not restricted */ \
1 << 10 | /* AF. 1:Accessed. This is to prevent access \
* fault when accessed for the first time */ \
@@ -51,7 +51,8 @@
0 << 1 | /* block/table. 0:block entry */ \
1 << 0 /* validity. 1:valid */ \
)
-#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2))
+#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2) | \
+ (1ULL << 53) | (1ULL << 54))
#define ATTR_WT (ATTR_BASE | (MAIR_INDX_WT << 2))
#define ATTR_WB (ATTR_BASE | (MAIR_INDX_WB << 2))
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