[coreboot-gerrit] Patch set updated for coreboot: d7565bd timestamps: Switch from tsc_t to uint64_t
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Jan 1 09:22:43 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8020
-gerrit
commit d7565bd112059bcaefb94a8adfbd7d346aa43cc9
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Thu Aug 1 13:31:44 2013 -0700
timestamps: Switch from tsc_t to uint64_t
Cherry-pick from chromium and adjusted for added boards
and changed directory layout for arch/arm.
Timestamp implementation for ARMv7
Abstract the use of rdtsc() and make the timestamps
uint64_t in the generic code.
The ARM implementation uses the monotonic timer.
Original-Signed-off-by: Stefan Reinauer <reinauer at google.com>
BRANCH=none
BUG=chrome-os-partner:18637
TEST=See cbmem print timestamps
Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62
Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793
(cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c)
Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/arm/armv7/Makefile.inc | 2 ++
src/arch/arm/armv7/timestamp.c | 29 ++++++++++++++++++
src/arch/x86/lib/Makefile.inc | 5 +++-
src/arch/x86/lib/timestamp.c | 27 +++++++++++++++++
src/include/cpu/x86/tsc.h | 5 ++++
src/include/timestamp.h | 12 +++++---
src/lib/hardwaremain.c | 2 +-
src/lib/timestamp.c | 25 +++++++---------
src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +-
src/mainboard/emulation/qemu-q35/romstage.c | 2 +-
src/mainboard/intel/cougar_canyon2/romstage.c | 41 ++++++++------------------
src/mainboard/lenovo/x201/romstage.c | 2 +-
src/mainboard/packardbell/ms2290/romstage.c | 2 +-
src/mainboard/via/epia-m850/romstage.c | 2 +-
src/soc/intel/baytrail/romstage/romstage.c | 22 +++-----------
src/soc/intel/broadwell/romstage/romstage.c | 22 +++-----------
src/soc/intel/fsp_baytrail/romstage/romstage.c | 19 +++++-------
src/southbridge/intel/bd82x6x/early_pch.c | 8 ++---
src/southbridge/intel/fsp_bd82x6x/bootblock.c | 2 +-
src/southbridge/intel/fsp_rangeley/romstage.c | 16 +++++-----
src/southbridge/intel/i82801gx/early_lpc.c | 7 ++---
src/southbridge/intel/lynxpoint/early_pch.c | 7 ++---
22 files changed, 137 insertions(+), 124 deletions(-)
diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc
index 62d5434..7e67178 100644
--- a/src/arch/arm/armv7/Makefile.inc
+++ b/src/arch/arm/armv7/Makefile.inc
@@ -57,6 +57,7 @@ romstage-y += cpu.S
romstage-y += exception.c
romstage-y += exception_asm.S
romstage-y += mmu.c
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
romstage-c-ccopts += $(armv7_flags)
romstage-S-ccopts += $(armv7_asm_flags)
@@ -74,6 +75,7 @@ ramstage-y += cpu.S
ramstage-y += exception.c
ramstage-y += exception_asm.S
ramstage-y += mmu.c
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-c-ccopts += $(armv7_flags)
ramstage-S-ccopts += $(armv7_asm_flags)
diff --git a/src/arch/arm/armv7/timestamp.c b/src/arch/arm/armv7/timestamp.c
new file mode 100644
index 0000000..07a209c
--- /dev/null
+++ b/src/arch/arm/armv7/timestamp.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <timestamp.h>
+#include <timer.h>
+
+uint64_t timestamp_get(void)
+{
+ struct mono_time timestamp;
+ timer_monotonic_get(×tamp);
+ return (uint64_t)timestamp.microseconds;
+}
+
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 22306f1..c7e8b62 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -24,6 +24,9 @@ ramstage-y += ebda.c
ramstage-y += rom_media.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
smm-y += memset.c
smm-y += memcpy.c
@@ -34,4 +37,4 @@ rmodules_x86_32-y += memset.c
rmodules_x86_32-y += memcpy.c
rmodules_x86_32-y += memmove.c
-endif # CONFIG_ARCH_RAMSTAGE_X86_32
\ No newline at end of file
+endif # CONFIG_ARCH_RAMSTAGE_X86_32
diff --git a/src/arch/x86/lib/timestamp.c b/src/arch/x86/lib/timestamp.c
new file mode 100644
index 0000000..02582a5
--- /dev/null
+++ b/src/arch/x86/lib/timestamp.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <cpu/x86/tsc.h>
+#include <timestamp.h>
+
+uint64_t timestamp_get(void)
+{
+ return rdtscll();
+}
+
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 7323599..71d253b 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -53,6 +53,11 @@ static inline unsigned long long rdtscll(void)
);
return val;
}
+
+static inline uint64_t tsc_to_uint64(tsc_t tstamp)
+{
+ return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
+}
#endif
#if CONFIG_TSC_CONSTANT_RATE
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index 66c1d9a..ba73135 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -20,6 +20,8 @@
#ifndef __TIMESTAMP_H__
#define __TIMESTAMP_H__
+#include <stdint.h>
+
struct timestamp_entry {
uint32_t entry_id;
uint64_t entry_stamp;
@@ -59,12 +61,10 @@ enum timestamp_id {
};
#if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
-#include <cpu/x86/tsc.h>
-void timestamp_init(tsc_t base);
-void timestamp_add(enum timestamp_id id, tsc_t ts_time);
+void timestamp_init(uint64_t base);
+void timestamp_add(enum timestamp_id id, uint64_t ts_time);
void timestamp_add_now(enum timestamp_id id);
void timestamp_reinit(void);
-tsc_t get_initial_timestamp(void);
#else
#define timestamp_init(base)
#define timestamp_add(id, time)
@@ -72,4 +72,8 @@ tsc_t get_initial_timestamp(void);
#define timestamp_reinit()
#endif
+/* Implemented by the architecture code */
+uint64_t timestamp_get(void);
+uint64_t get_initial_timestamp(void);
+
#endif
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index be052b3..e01247b 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -452,7 +452,7 @@ static void boot_state_schedule_static_entries(void)
void main(void)
{
/* Record current time, try to locate timestamps in CBMEM. */
- timestamp_init(rdtsc());
+ timestamp_init(timestamp_get());
timestamp_add_now(TS_START_RAMSTAGE);
post_code(POST_ENTRY_RAMSTAGE);
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index f0ee48d..67635f8 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -28,16 +28,11 @@
#define MAX_TIMESTAMPS 30
static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL;
-static tsc_t ts_basetime CAR_GLOBAL = { .lo = 0, .hi =0 };
+static uint64_t ts_basetime CAR_GLOBAL = 0;
-static void timestamp_stash(enum timestamp_id id, tsc_t ts_time);
+static void timestamp_stash(enum timestamp_id id, uint64_t ts_time);
-static uint64_t tsc_to_uint64(tsc_t tstamp)
-{
- return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
-}
-
-static void timestamp_real_init(tsc_t base)
+static void timestamp_real_init(uint64_t base)
{
struct timestamp_table* tst;
@@ -50,14 +45,14 @@ static void timestamp_real_init(tsc_t base)
return;
}
- tst->base_time = tsc_to_uint64(base);
+ tst->base_time = base;
tst->max_entries = MAX_TIMESTAMPS;
tst->num_entries = 0;
car_set_var(ts_table_p, tst);
}
-void timestamp_add(enum timestamp_id id, tsc_t ts_time)
+void timestamp_add(enum timestamp_id id, uint64_t ts_time)
{
struct timestamp_entry *tse;
struct timestamp_table *ts_table = NULL;
@@ -75,18 +70,18 @@ void timestamp_add(enum timestamp_id id, tsc_t ts_time)
tse = &ts_table->entries[ts_table->num_entries++];
tse->entry_id = id;
- tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time;
+ tse->entry_stamp = ts_time - ts_table->base_time;
}
void timestamp_add_now(enum timestamp_id id)
{
- timestamp_add(id, rdtsc());
+ timestamp_add(id, timestamp_get());
}
#define MAX_TIMESTAMP_CACHE 8
struct timestamp_cache {
enum timestamp_id id;
- tsc_t time;
+ uint64_t time;
} timestamp_cache[MAX_TIMESTAMP_CACHE] CAR_GLOBAL;
static int timestamp_entries CAR_GLOBAL = 0;
@@ -99,7 +94,7 @@ static int timestamp_entries CAR_GLOBAL = 0;
* part of CAR migration for romstage, and in ramstage main().
*/
-static void timestamp_stash(enum timestamp_id id, tsc_t ts_time)
+static void timestamp_stash(enum timestamp_id id, uint64_t ts_time)
{
struct timestamp_cache *ts_cache = car_get_var(timestamp_cache);
int ts_entries = car_get_var(timestamp_entries);
@@ -124,7 +119,7 @@ static void timestamp_do_sync(void)
car_set_var(timestamp_entries, 0);
}
-void timestamp_init(tsc_t base)
+void timestamp_init(uint64_t base)
{
if (!boot_cpu())
return;
diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c
index c617a0a..8992a57 100644
--- a/src/mainboard/emulation/qemu-i440fx/romstage.c
+++ b/src/mainboard/emulation/qemu-i440fx/romstage.c
@@ -50,7 +50,7 @@ void main(unsigned long bist)
cbmem_was_initted = !cbmem_recovery(0);
- timestamp_init(rdtsc());
+ timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
}
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
index 658051c..6f08b6a 100644
--- a/src/mainboard/emulation/qemu-q35/romstage.c
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -52,7 +52,7 @@ void main(unsigned long bist)
cbmem_was_initted = !cbmem_recovery(0);
- timestamp_init(rdtsc());
+ timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
}
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 6580ab9..0823ae2 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -183,14 +183,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x40);
#if CONFIG_COLLECT_TIMESTAMPS
- tsc_t start_romstage_time;
- tsc_t before_initram_time;
-
- start_romstage_time = rdtsc();
-
+ uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4);
/* since this mainboard doesn't use audio, we can stuff the TSC values in there */
- pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time.lo >> 4 |
- start_romstage_time.lo << 28);
+ pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time);
#endif
pch_enable_lpc();
@@ -240,11 +235,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48);
#if CONFIG_COLLECT_TIMESTAMPS
- before_initram_time= rdtsc();
+ uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4);
/* since this mainboard doesn't use audio, we can stuff the TSC values in there */
- pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time.lo >> 4 |
- before_initram_time.lo << 28);
-
+ pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time);
#endif
/*
@@ -267,20 +260,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
void *cbmem_hob_ptr;
#if CONFIG_COLLECT_TIMESTAMPS
- tsc_t start_romstage_time;
- tsc_t base_time;
- tsc_t before_initram_time;
- tsc_t after_initram_time = rdtsc();
- u32 timebase = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0);
- u32 time_romstage_start = pci_read_config32(PCI_DEV(0, 27, 0), 0x2c);
- u32 time_before_initram = pci_read_config32(PCI_DEV(0, 27, 0), 0x14);
-
- base_time.lo = timebase << 4;
- base_time.hi = timebase >> 28;
- start_romstage_time.lo = time_romstage_start << 4;
- start_romstage_time.hi = time_romstage_start >> 28;
- before_initram_time.lo = time_before_initram << 4;
- before_initram_time.hi = time_before_initram >> 28;
+ uint64_t after_initram_time = timestamp_get();
+ uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4;
+ uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4;
#endif
/*
@@ -335,13 +317,11 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
*(u32*)cbmem_hob_ptr = (u32)HobListPtr;
post_code(0x4f);
-#if CONFIG_COLLECT_TIMESTAMPS
- timestamp_init(base_time);
+ timestamp_init(get_initial_timestamp());
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_initram_time );
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE);
-#endif
/* Load the ramstage. */
copy_and_run();
@@ -353,3 +333,8 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
/* No overrides needed */
return;
}
+
+uint64_t get_initial_timestamp(void)
+{
+ return (uint64_t) pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 4;
+}
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index e58f5f6..be49067 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -190,7 +190,7 @@ void main(unsigned long bist)
int s3resume = 0;
const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
- timestamp_init(rdtsc ());
+ timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index ca96c87..fbbd4b5 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -175,7 +175,7 @@ void main(unsigned long bist)
int s3resume = 0;
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
- timestamp_init(rdtsc ());
+ timestamp_init(timestamp_get());
/* SERR pin is confused on reset. Clear NMI. */
outb(4, 0x61);
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 899c5a6..01d955a 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -46,7 +46,7 @@ void main(unsigned long bist)
{
u32 tolm;
- timestamp_init(rdtsc());
+ timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* First thing we need to do on the VX900, before anything else */
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index b69b532..ac5afab 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -44,20 +44,6 @@
#include <baytrail/smm.h>
#include <baytrail/spi.h>
-static inline uint64_t timestamp_get(void)
-{
- return rdtscll();
-}
-
-static inline tsc_t ts64_to_tsc(uint64_t ts)
-{
- tsc_t tsc = {
- .lo = ts,
- .hi = ts >> 32,
- };
- return tsc;
-}
-
/* The cache-as-ram assembly file calls romstage_main() after setting up
* cache-as-ram. romstage_main() will then call the mainboards's
* mainboard_romstage_entry() function. That function then calls
@@ -274,10 +260,10 @@ void romstage_common(struct romstage_params *params)
chromeos_init(prev_sleep_state);
/* Save timestamp information. */
- timestamp_init(ts64_to_tsc(params->ts.times[0]));
- timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
- timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
- timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
+ timestamp_init(params->ts.times[0]);
+ timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
+ timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
+ timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
}
void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 4a5a47c..f234fda 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -38,20 +38,6 @@
#include <broadwell/romstage.h>
#include <broadwell/spi.h>
-static inline uint64_t timestamp_get(void)
-{
- return rdtscll();
-}
-
-static inline tsc_t ts64_to_tsc(uint64_t ts)
-{
- tsc_t tsc = {
- .lo = ts,
- .hi = ts >> 32,
- };
- return tsc;
-}
-
static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
{
struct romstage_timestamps *rt = &rp->ts;
@@ -142,10 +128,10 @@ void romstage_common(struct romstage_params *params)
chromeos_init(params->power_state->prev_sleep_state);
/* Save timestamp information. */
- timestamp_init(ts64_to_tsc(params->ts.times[0]));
- timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
- timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
- timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
+ timestamp_init(params->ts.times[0]);
+ timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
+ timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
+ timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
}
void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 2619c96..ad42e73 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -221,10 +221,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
struct romstage_handoff *handoff;
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- tsc_t after_initram_time = rdtsc();
- tsc_t base_time;
- base_time.hi = 0;
- base_time.lo = 0;
+ uint64_t after_initram_time = timestamp_get();
#endif
post_code(0x4a);
@@ -244,9 +241,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
report_platform_info();
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- after_initram_time = rdtsc();
-#endif
post_code(0x4b);
late_mainboard_romstage_entry();
@@ -271,13 +265,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
-
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- timestamp_init(base_time);
- timestamp_reinit();
+ timestamp_init(get_initial_timestamp());
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE);
-#endif
post_code(0x4f);
@@ -285,3 +275,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
copy_and_run();
while (1);
}
+
+uint64_t get_initial_timestamp(void)
+{
+ return 0;
+}
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 3438a0a..95182ce 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -20,21 +20,19 @@
#include <arch/io.h>
#include <timestamp.h>
+#include <cpu/x86/tsc.h>
#include "pch.h"
#include <arch/acpi.h>
#include <console/console.h>
-#if CONFIG_COLLECT_TIMESTAMPS
-tsc_t get_initial_timestamp(void)
+uint64_t get_initial_timestamp(void)
{
tsc_t base_time = {
.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
};
- return base_time;
+ return tsc_to_uint64(base_time);
}
-#endif
-
int southbridge_detect_s3_resume(void)
{
diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
index 61ff301..9b3e97a 100644
--- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c
+++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
@@ -34,7 +34,7 @@ static void store_initial_timestamp(void)
* only storing the low nibble of the high dword of the tsc. Even this
* is probably 0 by the time we get here, so storing 64 bits is overkill.S
*/
- pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28);
+ pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28);
}
/*
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 6c5751e..fba9eb6 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -95,11 +95,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
void *cbmem_hob_ptr;
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- tsc_t after_initram_time = rdtsc();
- tsc_t base_time;
- base_time.hi = 0;
- base_time.lo = 0;
+ uint64_t after_initram_time = timestamp_get();
#endif
+
post_code(0x48);
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
@@ -129,12 +127,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e);
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- timestamp_init(base_time);
- timestamp_reinit();
+ timestamp_init(get_initial_timestamp());
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE);
-#endif
post_code(0x4f);
@@ -142,3 +137,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
copy_and_run();
while (1);
}
+
+uint64_t get_initial_timestamp(void)
+{
+ return 0;
+}
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c
index 69bbfb2..b08a964 100644
--- a/src/southbridge/intel/i82801gx/early_lpc.c
+++ b/src/southbridge/intel/i82801gx/early_lpc.c
@@ -20,20 +20,19 @@
#include <arch/io.h>
#include <timestamp.h>
+#include <cpu/x86/tsc.h>
#include <console/console.h>
#include <arch/acpi.h>
#include "i82801gx.h"
-#if CONFIG_COLLECT_TIMESTAMPS
-tsc_t get_initial_timestamp(void)
+uint64_t get_initial_timestamp(void)
{
tsc_t base_time = {
.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
};
- return base_time;
+ return tsc_to_uint64(base_time);
}
-#endif
int southbridge_detect_s3_resume(void)
{
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index fdbb2a3..5378428 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -23,6 +23,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <timestamp.h>
+#include <cpu/x86/tsc.h>
#include <elog.h>
#include "pch.h"
#include "chip.h"
@@ -71,16 +72,14 @@ static void pch_generic_setup(void)
printk(BIOS_DEBUG, " done.\n");
}
-#if CONFIG_COLLECT_TIMESTAMPS
-tsc_t get_initial_timestamp(void)
+uint64_t get_initial_timestamp(void)
{
tsc_t base_time = {
.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
};
- return base_time;
+ return tsc_to_uint64(base_time);
}
-#endif
static int sleep_type_s3(void)
{
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