[coreboot-gerrit] Patch set updated for coreboot: be15366 [NOTFORMERGE] Intel FSP: Timestamps

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8024

-gerrit

commit be15366a3997bbdffefa002792e8cb366e078c00
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Dec 31 21:48:48 2014 +0200

    [NOTFORMERGE] Intel FSP: Timestamps
    
    Only after BROKEN_CAR_MIGRATE is fixed.
    
    Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/intel/cougar_canyon2/romstage.c  | 23 ++++-------------------
 src/soc/intel/fsp_baytrail/romstage/romstage.c | 11 ++++++-----
 src/southbridge/intel/fsp_rangeley/romstage.c  | 11 ++++++-----
 3 files changed, 16 insertions(+), 29 deletions(-)

diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 0823ae2..02a00eb 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -182,11 +182,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 
 	post_code(0x40);
 
-#if CONFIG_COLLECT_TIMESTAMPS
-	uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4);
-	/* since this mainboard doesn't use audio, we can stuff the TSC values in there */
-	pci_write_config32(PCI_DEV(0, 27, 0), 0x2c,  start_romstage_time);
-#endif
+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
 
 	pch_enable_lpc();
 
@@ -234,11 +231,7 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 
 	post_code(0x48);
 
-#if CONFIG_COLLECT_TIMESTAMPS
-	uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4);
-	/* since this mainboard doesn't use audio, we can stuff the TSC values in there */
-	pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time);
-#endif
+	timestamp_add_now(TS_BEFORE_INITRAM);
 
   /*
    * Call early init to initialize memory and chipset. This function returns
@@ -259,11 +252,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	u32 reg32;
 	void *cbmem_hob_ptr;
 
-#if CONFIG_COLLECT_TIMESTAMPS
-	uint64_t after_initram_time = timestamp_get();
-	uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4;
-	uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4;
-#endif
+	timestamp_add_now(TS_AFTER_INITRAM);
 
 	/*
 	 * HD AUDIO is not used on this system, so we're using some registers
@@ -317,10 +306,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	*(u32*)cbmem_hob_ptr = (u32)HobListPtr;
 	post_code(0x4f);
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
-	timestamp_add(TS_BEFORE_INITRAM, before_initram_time );
-	timestamp_add(TS_AFTER_INITRAM, after_initram_time);
 	timestamp_add_now(TS_END_ROMSTAGE);
 
 	/* Load the ramstage. */
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index ad42e73..f18daef 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -161,6 +161,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 
 	post_code(0x40);
 
+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
 	program_base_addresses();
 
 	post_code(0x41);
@@ -199,6 +202,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 
 	post_code(0x47);
 
+	timestamp_add_now(TS_BEFORE_INITRAM);
+
   /*
    * Call early init to initialize memory and chipset. This function returns
    * to the romstage_main_continue function with a pointer to the HOB
@@ -220,9 +225,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	uint32_t prev_sleep_state;
 	struct romstage_handoff *handoff;
 
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
-	uint64_t after_initram_time = timestamp_get();
-#endif
+	timestamp_add_now(TS_AFTER_INITRAM);
 
 	post_code(0x4a);
 	printk(BIOS_DEBUG, "%s status: %x  hob_list_ptr: %x\n",
@@ -265,8 +268,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add(TS_AFTER_INITRAM, after_initram_time);
 	timestamp_add_now(TS_END_ROMSTAGE);
 
 	post_code(0x4f);
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index fba9eb6..a668815 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -53,6 +53,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 	 */
 	outb(0x40, 0x80);
 
+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
 	/* Rangeley UART POR state is enabled */
 	console_init();
 	post_code(0x41);
@@ -75,6 +78,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 		read32(func_dis);
 	}
 
+	timestamp_add_now(TS_BEFORE_INITRAM);
+
   /*
    * Call early init to initialize memory and chipset. This function returns
    * to the romstage_main_continue function with a pointer to the HOB
@@ -94,9 +99,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	int cbmem_was_initted;
 	void *cbmem_hob_ptr;
 
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
-	uint64_t after_initram_time = timestamp_get();
-#endif
+	timestamp_add_now(TS_AFTER_INITRAM);
 
 	post_code(0x48);
 	printk(BIOS_DEBUG, "%s status: %x  hob_list_ptr: %x\n",
@@ -127,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
 	post_code(0x4e);
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add(TS_AFTER_INITRAM, after_initram_time);
 	timestamp_add_now(TS_END_ROMSTAGE);
 
 	post_code(0x4f);