[coreboot-gerrit] Patch set updated for coreboot: cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Mon Dec 28 13:19:25 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12063
-gerrit
commit 162a8c4187ed28357798a3cbf46eddfb7ab5ee18
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Fri Aug 28 20:48:17 2015 -0500
cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure
Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/Kconfig | 4 ++++
src/arch/x86/include/arch/smp/spinlock.h | 7 ++++++-
src/cpu/amd/microcode/microcode.c | 24 +++++++++++++++++++++++-
3 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 38cf855..2b9ef7c 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -488,6 +488,10 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
SR565x, that cannot handle concurrent CBFS accesses from
multiple APs during early startup.
+config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
+ bool
+ default n
+
config HAVE_MONOTONIC_TIMER
def_bool n
help
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
index 057d9e3..39a81d2 100644
--- a/src/arch/x86/include/arch/smp/spinlock.h
+++ b/src/arch/x86/include/arch/smp/spinlock.h
@@ -1,7 +1,10 @@
#ifndef ARCH_SMP_SPINLOCK_H
#define ARCH_SMP_SPINLOCK_H
-#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)
+#if !defined(__PRE_RAM__) \
+ || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
+ || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
+ || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
/*
* Your basic SMP spinlocks, allowing only a single CPU anywhere
@@ -16,6 +19,8 @@ spinlock_t *romstage_console_lock(void);
void initialize_romstage_console_lock(void);
spinlock_t* romstage_nvram_cbfs_lock(void);
void initialize_romstage_nvram_cbfs_lock(void);
+spinlock_t* romstage_microcode_cbfs_lock(void);
+void initialize_romstage_microcode_cbfs_lock(void);
#endif
#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 37d395a..5f3280c 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -21,6 +21,12 @@
#include <cbfs.h>
#include <arch/io.h>
+#ifdef __PRE_RAM__
+#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#include <smp/spinlock.h>
+#endif
+#endif
+
#define UCODE_DEBUG(fmt, args...) \
do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0)
@@ -197,14 +203,30 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
return;
}
+#ifdef __PRE_RAM__
+#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+ spin_lock(romstage_microcode_cbfs_lock());
+#endif
+#endif
+
ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i],
CBFS_TYPE_MICROCODE, &ucode_len);
if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n");
-
+#ifdef __PRE_RAM__
+#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+ spin_unlock(romstage_microcode_cbfs_lock());
+#endif
+#endif
return;
}
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
+
+#ifdef __PRE_RAM__
+#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+ spin_unlock(romstage_microcode_cbfs_lock());
+#endif
+#endif
}
}
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