[coreboot-gerrit] Patch set updated for coreboot: broadwell: Fix SATA Gen3 DTLE configuration registers
Duncan Laurie (dlaurie@google.com)
gerrit at coreboot.org
Sun Dec 27 03:47:05 CET 2015
Duncan Laurie (dlaurie at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12793
-gerrit
commit 38bdcdcd834537107ed2f01b3105ada31204ff57
Author: Duncan Laurie <dlaurie at google.com>
Date: Tue Dec 22 17:09:16 2015 -0800
broadwell: Fix SATA Gen3 DTLE configuration registers
The port0 and port1 registers were swapped, which meant it did
not work to apply the DTLE settings to the correct SATA port.
This was tested on an unreleased mainboard but is verified with
the documentation to be the correct register addresses now.
Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da
Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
src/soc/intel/broadwell/include/soc/sata.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/soc/intel/broadwell/include/soc/sata.h
index 987bc3c..d1aa45d 100644
--- a/src/soc/intel/broadwell/include/soc/sata.h
+++ b/src/soc/intel/broadwell/include/soc/sata.h
@@ -27,10 +27,10 @@
#define SATA_SECRT88_VADJ_MASK 0xff
#define SATA_SECRT88_VADJ_SHIFT 16
-#define SATA_IOBP_SP0DTLE_DATA 0xea002550
-#define SATA_IOBP_SP0DTLE_EDGE 0xea002554
-#define SATA_IOBP_SP1DTLE_DATA 0xea002750
-#define SATA_IOBP_SP1DTLE_EDGE 0xea002754
+#define SATA_IOBP_SP0DTLE_DATA 0xea002750
+#define SATA_IOBP_SP0DTLE_EDGE 0xea002754
+#define SATA_IOBP_SP1DTLE_DATA 0xea002550
+#define SATA_IOBP_SP1DTLE_EDGE 0xea002554
#define SATA_DTLE_MASK 0xF
#define SATA_DTLE_DATA_SHIFT 24
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