[coreboot-gerrit] Patch merged into coreboot/master: imgtec/pistachio: DDR2, DDR3: DLL reset set
gerrit at coreboot.org
gerrit at coreboot.org
Mon Dec 21 02:06:19 CET 2015
the following patch was just integrated into master:
commit 721f2998a5d4143f7d609e79255d570b43d804a4
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Tue May 26 12:20:19 2015 +0100
imgtec/pistachio: DDR2, DDR3: DLL reset set
Bit 8 of the MR register is automatically set by the PHY
during memory initilization but having it set in the
register leads to a more clear understanding.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
Reviewed-on: https://review.coreboot.org/12764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
See https://review.coreboot.org/12764 for details.
-gerrit
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