[coreboot-gerrit] New patch to review for coreboot: imgtec/pistachio: memlayout: update GRAM size
Ionela Voinescu (ionela.voinescu@imgtec.com)
gerrit at coreboot.org
Thu Dec 17 21:08:35 CET 2015
Ionela Voinescu (ionela.voinescu at imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12772
-gerrit
commit e5d41d543a2977cf6a54b51f777994803689fbf5
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Sun Nov 1 16:36:35 2015 +0000
imgtec/pistachio: memlayout: update GRAM size
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role
of SRAM) was placed at a 4K aligned address, resulting in a size of
408KB.
Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d
Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index a0b48b2..c84de40 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -39,7 +39,7 @@ SECTIONS
ROMSTAGE(0x1a005000, 40K)
VBOOT2_WORK(0x1a00f000, 12K)
PRERAM_CBFS_CACHE(0x1a012000, 56K)
- SRAM_END(0x1a020000)
+ SRAM_END(0x1a066000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.
* This is identical to SRAM above, and thus also limited 64K and
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