[coreboot-gerrit] New patch to review for coreboot: Cyan: Update DPTF parameters for higher temperature
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Wed Dec 16 20:30:41 CET 2015
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12747
-gerrit
commit 1da2f0b246d189ccb30bfb543bae5577368fd3c8
Author: T.H.Lin <T.H_Lin at quantatw.com>
Date: Thu Aug 27 17:18:47 2015 +0800
Cyan: Update DPTF parameters for higher temperature
TEST=Run DPTF
Reviewed-on: https://chromium-review.googlesource.com/295478
Tested-by: T.H. Lin <T.H_Lin at quantatw.com>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Commit-Queue: T.H. Lin <T.H_Lin at quantatw.com>
Change-Id: Ifa58ad72105d377c00df577f0e16ff1148b70119
Signed-off-by: T.H. Lin <T.H_Lin at quantatw.com>
---
src/mainboard/google/cyan/acpi/dptf.asl | 29 ++++++++---------------------
src/mainboard/google/cyan/onboard.h | 5 +++++
2 files changed, 13 insertions(+), 21 deletions(-)
diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl
index ffa8886..95b6951 100755
--- a/src/mainboard/google/cyan/acpi/dptf.asl
+++ b/src/mainboard/google/cyan/acpi/dptf.asl
@@ -16,20 +16,18 @@
#define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
-#define DPTF_TSR0_PASSIVE 48
-#define DPTF_TSR0_CRITICAL 70
-
+#define DPTF_TSR0_PASSIVE 49
+#define DPTF_TSR0_CRITICAL 75
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
-#define DPTF_TSR1_PASSIVE 60
-#define DPTF_TSR1_CRITICAL 70
+#define DPTF_TSR1_PASSIVE 65
+#define DPTF_TSR1_CRITICAL 85
#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
-#define DPTF_TSR2_PASSIVE 55
-#define DPTF_TSR2_CRITICAL 70
-
+#define DPTF_TSR2_PASSIVE 49
+#define DPTF_TSR2_CRITICAL 75
#define DPTF_ENABLE_CHARGER
@@ -50,18 +48,7 @@ Name (DTRT, Package () {
Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 0 */
- Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
-
-#ifdef DPTF_ENABLE_CHARGER
- /* Charger Effect on Temp Sensor 1 */
- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
-#endif
-
- /* CPU Effect on Temp Sensor 1 */
- Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
-
- /* CPU Effect on Temp Sensor 2 */
- Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
})
Name (MPPC, Package ()
@@ -69,7 +56,7 @@ Name (MPPC, Package ()
0x2, /* Revision */
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
- 1600, /* PowerLimitMinimum */
+ 2000, /* PowerLimitMinimum */
6200, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */
diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h
index fdb1c8e..d46fd21 100755
--- a/src/mainboard/google/cyan/onboard.h
+++ b/src/mainboard/google/cyan/onboard.h
@@ -78,3 +78,8 @@
#define BOARD_PRE_EVT 0x01
#define BOARD_EVT 0x02
#endif
+
+
+#define DPTF_CPU_PASSIVE 88
+#define DPTF_CPU_CRITICAL 90
+
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