[coreboot-gerrit] New patch to review for coreboot: mediatek/mt8173: Add mtcmos power-on control for audio and display
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Dec 1 19:58:09 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12617
-gerrit
commit 6b0f68c47c15fddd19fb7cbada604e755032d3ac
Author: CC Ma <cc.ma at mediatek.com>
Date: Fri Jul 31 17:10:59 2015 +0800
mediatek/mt8173: Add mtcmos power-on control for audio and display
BRANCH=none
BUG=none
TEST=none
Change-Id: Ic046c66c8e314bd61f96c2edbc5d832260590afe
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 84de3a6f1a726938e2318814d6faaf6a7dd29ac0
Original-Change-Id: If29f28a092617532dd73e71e0dbe24fd930c3bf8
Original-Signed-off-by: CC Ma <cc.ma at mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292677
Original-Commit-Ready: Yidi Lin <yidi.lin at mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/soc/mediatek/mt8173/include/soc/mtcmos.h | 25 +++++++++
src/soc/mediatek/mt8173/mtcmos.c | 76 ++++++++++++++++++++++++++++
2 files changed, 101 insertions(+)
diff --git a/src/soc/mediatek/mt8173/include/soc/mtcmos.h b/src/soc/mediatek/mt8173/include/soc/mtcmos.h
new file mode 100644
index 0000000..4a27a1b
--- /dev/null
+++ b/src/soc/mediatek/mt8173/include/soc/mtcmos.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_MEDIATEK_MT8173_MTCMOS_H__
+#define __SOC_MEDIATEK_MT8173_MTCMOS_H__
+
+void mtcmos_audio_power_on(void);
+void mtcmos_display_power_on(void);
+#endif /* __SOC_MEDIATEK_MT8173_MTCMOS_H__ */
diff --git a/src/soc/mediatek/mt8173/mtcmos.c b/src/soc/mediatek/mt8173/mtcmos.c
new file mode 100644
index 0000000..b4edea6
--- /dev/null
+++ b/src/soc/mediatek/mt8173/mtcmos.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/mtcmos.h>
+#include <soc/spm.h>
+
+enum {
+ SRAM_ISOINT_B = 1U << 6,
+ SRAM_CKISO = 1U << 5,
+ PWR_CLK_DIS = 1U << 4,
+ PWR_ON_2ND = 1U << 3,
+ PWR_ON = 1U << 2,
+ PWR_ISO = 1U << 1,
+ PWR_RST_B = 1U << 0
+};
+
+enum {
+ SRAM_PDN = 0xf << 8,
+ DIS_SRAM_ACK = 0x1 << 12,
+ AUD_SRAM_ACK = 0xf << 12,
+};
+
+enum {
+ DIS_PWR_STA_MASK = 0x1 << 3,
+ AUD_PWR_STA_MASK = 0x1 << 24,
+};
+
+static void mtcmos_power_on(u32 *pwr_con, u32 pwr_sta_mask)
+{
+ write32(&mt8173_spm->poweron_config_set,
+ (SPM_PROJECT_CODE << 16) | (1U << 0));
+
+ setbits_le32(pwr_con, PWR_ON);
+ setbits_le32(pwr_con, PWR_ON_2ND);
+
+ while (!(read32(&mt8173_spm->pwr_status) & pwr_sta_mask) ||
+ !(read32(&mt8173_spm->pwr_status_2nd) & pwr_sta_mask))
+ continue;
+
+ clrbits_le32(pwr_con, PWR_CLK_DIS);
+ clrbits_le32(pwr_con, PWR_ISO);
+ setbits_le32(pwr_con, PWR_RST_B);
+ clrbits_le32(pwr_con, SRAM_PDN);
+}
+
+void mtcmos_audio_power_on(void)
+{
+ mtcmos_power_on(&mt8173_spm->audio_pwr_con, AUD_PWR_STA_MASK);
+ while (read32(&mt8173_spm->audio_pwr_con) & AUD_SRAM_ACK)
+ continue;
+}
+
+void mtcmos_display_power_on(void)
+{
+ mtcmos_power_on(&mt8173_spm->dis_pwr_con, DIS_PWR_STA_MASK);
+ while (read32(&mt8173_spm->dis_pwr_con) & DIS_SRAM_ACK)
+ continue;
+}
+
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