[coreboot-gerrit] New patch to review for coreboot: google/chell: Update mainboard for EVT
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Dec 1 19:57:41 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12598
-gerrit
commit 6cb73e1ce7cfefeb91c2bdbcfa583af422ec36c7
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Sat Nov 21 18:43:18 2015 -0800
google/chell: Update mainboard for EVT
- Disable kepler device, it is removed and was not used on proto anyway.
- Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM.
- Disable HS400, this is breaking some devices on proto boards and
is being disabled to reduce risk for EVT build.
- Change Type-C USB2 port drive strength.
BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell proto
Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180
Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010
Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313825
Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/chell/devicetree.cb | 15 ++++++---------
src/mainboard/google/chell/gpio.h | 6 +++---
2 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index e76b015..9bd06b2 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -35,7 +35,7 @@ chip soc/intel/skylake
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
- register "ScsEmmcHs400Enabled" = "1"
+ register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "2"
register "IshEnable" = "0"
register "PttSwitch" = "0"
@@ -43,18 +43,15 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
- # Enable Root port 1 and 5.
+ # Enable Root port 1.
register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[0]" = "1"
- register "PcieRpClkReqSupport[4]" = "1"
- # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
+ # RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
- register "PcieRpClkReqNumber[4]" = "2"
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2
+ register "usb2_ports[0]" = "USB2_PORT_LONG" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_LONG" # Type-C Port 2
register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port
register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera
@@ -106,7 +103,7 @@ chip soc/intel/skylake
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h
index a347454..c6e07a6 100644
--- a/src/mainboard/google/chell/gpio.h
+++ b/src/mainboard/google/chell/gpio.h
@@ -118,7 +118,7 @@ static const struct pad_config gpio_table[] = {
/* UART0_RXD */ /* GPP_C8 */
/* UART0_TXD */ /* GPP_C9 */
/* UART0_RTS# */ /* GPP_C10 */
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
@@ -153,7 +153,7 @@ static const struct pad_config gpio_table[] = {
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* SPI1_IO2 */ /* GPP_D21 */
-/* SPI1_IO3 */ /* GPP_D22 */
+/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */
/* SATAXPCIE1 */ /* GPP_E1 */
@@ -233,7 +233,7 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
};
#endif
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