[coreboot-gerrit] Patch set updated for coreboot: southbridge/amd/sb700: Fix boot hang when AHCI mode disabled
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Tue Dec 1 16:13:35 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12572
-gerrit
commit a276cddfc62bd869a92c9ed6b58d58de277d77b0
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Sun Oct 25 18:58:24 2015 -0500
southbridge/amd/sb700: Fix boot hang when AHCI mode disabled
Existence of requested PCI device was not checked when enabling
IDE mode on the SP5100. Fix incorrect PCI device ID and check
for device existence before attempting setup.
Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/southbridge/amd/sb700/early_setup.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index f7e9120..06c6c77 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -520,26 +520,28 @@ static void sb700_devices_por_init(void)
if (!sata_ahci_mode){
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
/* SP5100 default SATA mode is RAID5 MODE */
- dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0);
+ dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0);
- /* Set SATA Operation Mode, Set to IDE mode */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 0);
- pci_write_config8(dev, 0x40, byte);
+ if (dev != PCI_DEV_INVALID) {
+ /* Set SATA Operation Mode, Set to IDE mode */
+ byte = pci_read_config8(dev, 0x40);
+ byte |= (1 << 0);
+ pci_write_config8(dev, 0x40, byte);
- dword = 0x01018f00;
- pci_write_config32(dev, 0x8, dword);
+ dword = 0x01018f00;
+ pci_write_config32(dev, 0x8, dword);
- /* set SATA Device ID writable */
- dword = pci_read_config32(dev, 0x40);
- dword &= ~(1 << 24);
- pci_write_config32(dev, 0x40, dword);
+ /* set SATA Device ID writable */
+ dword = pci_read_config32(dev, 0x40);
+ dword &= ~(1 << 24);
+ pci_write_config32(dev, 0x40, dword);
- /* set Device ID consistent with IDE emulation mode configuration */
- pci_write_config32(dev, 0x0, 0x43901002);
+ /* set Device ID consistent with IDE emulation mode configuration */
+ pci_write_config32(dev, 0x0, 0x43901002);
- /* rpr v2.13 4.17 Reset CPU on Sync Flood */
- abcfg_reg(0x10050, 1 << 2, 1 << 2);
+ /* rpr v2.13 4.17 Reset CPU on Sync Flood */
+ abcfg_reg(0x10050, 1 << 2, 1 << 2);
+ }
#endif
}
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