[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Implement HW Sequence based WP status read functionality
gerrit at coreboot.org
gerrit at coreboot.org
Sat Aug 29 09:24:34 CEST 2015
the following patch was just integrated into master:
commit 7a2defb2ddc0e2872f00bfcdc7c383ed89a55097
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date: Wed Aug 19 14:15:32 2015 +0530
intel/skylake: Implement HW Sequence based WP status read functionality
Early(romstage) SPI write protected status read(wpsr) functionality
was broken causing 2 sec timeout issue.Implementing HW Seq based rd
status operation in romstage.
BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and tested using below command
flashrom -p host --wp-enable [this should enable WP on flash chip]
Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked)
flashrom -p host --wp-disable [this should disable WP on flash chip]
Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked)
Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488
Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677
Original-Signed-off-by: Subrata <subrata.banik at intel.com>
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294445
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: http://review.coreboot.org/11423
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
See http://review.coreboot.org/11423 for details.
-gerrit
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