[coreboot-gerrit] New patch to review for coreboot: AMD bettong: Fix the PCIe lane map

[Zheng Bao (zheng.bao@amd.com)]

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11375

-gerrit

commit 47a97e319d18f6b69ffed2a7aade49f5585cba2e
Author: zbao <fishbaozi at gmail.com>
Date:   Sun Aug 16 22:45:59 2015 -0400

    AMD bettong: Fix the PCIe lane map
    
    Change-Id: Ieaed5cf76c6f0a6a121e6add731d5c1e1528dfc7
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/mainboard/amd/bettong/PlatformGnbPcie.c | 27 +++++++++++++++++++--------
 src/mainboard/amd/bettong/devicetree.cb     |  2 ++
 2 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/amd/bettong/PlatformGnbPcie.c b/src/mainboard/amd/bettong/PlatformGnbPcie.c
index af272dd..16ac427 100644
--- a/src/mainboard/amd/bettong/PlatformGnbPcie.c
+++ b/src/mainboard/amd/bettong/PlatformGnbPcie.c
@@ -22,7 +22,7 @@
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
-	/* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 2, ...) */
+	/* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
@@ -46,33 +46,44 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
 	/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
 	{
 		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+		PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4,
 				HotplugDisabled,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x04, 0)
 	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */
 	{
 		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+		PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 5, 5),
 		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
 				HotplugDisabled,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x05, 0)
 	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+	/* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */
 	{
-		DESCRIPTOR_TERMINATE_LIST, // Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
 		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
 				HotplugDisabled,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x06, 0)
 	},
+	/* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */
+	{
+		DESCRIPTOR_TERMINATE_LIST, // Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x07, 0)
+	},
+
 };
 
 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb
index 44ae75a..90b0324 100644
--- a/src/mainboard/amd/bettong/devicetree.cb
+++ b/src/mainboard/amd/bettong/devicetree.cb
@@ -37,6 +37,8 @@ chip northbridge/amd/pi/00660F01/root_complex
 				device pci 2.3 on  end # Realtek NIC
 				device pci 2.4 on  end # Edge Connector
 				device pci 2.5 on  end # Edge Connector
+				device pci 3.0 on  end # Edge Connector
+				device pci 3.1 on  end # Edge Connector
 			end	#chip northbridge/amd/pi/00660F01
 
 			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus