[coreboot-gerrit] New patch to review for coreboot: d5eef7a imgtech/pistachio: Give some more space to the bootblock

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10035

-gerrit

commit d5eef7aaffbb2668213750149a7bed94d0553278
Author: Patrick Georgi <pgeorgi at chromium.org>
Date:   Wed Apr 29 21:19:00 2015 +0200

    imgtech/pistachio: Give some more space to the bootblock
    
    The memory layout isn't very clear here, since there are two
    regions (bootblock and "SRAM") that are actually the same.
    So when increasing the bootblock's size, we also need to move
    the romstage around.
    
    Change-Id: Ib158a4ef96b7c1dd1132b6e8bd47a0eb9c3951d9
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index c7ea04b..e9f6c59 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,12 +38,12 @@ SECTIONS
 	 * and then through the identity mapping in ROM stage.
 	 */
 	SRAM_START(0x1a000000)
-	ROMSTAGE(0x1a004800, 36K)
-	PRERAM_CBFS_CACHE(0x1a00d800, 74K)
+	ROMSTAGE(0x1a005000, 36K)
+	PRERAM_CBFS_CACHE(0x1a00e000, 72K)
 	SRAM_END(0x1a020000)
 
 	/* Bootblock executes out of KSEG0 and sets up the identity mapping. */
-	BOOTBLOCK(0x9a000000, 18K)
+	BOOTBLOCK(0x9a000000, 20K)
 
 	/*
 	 * Let's use SRAM for stack and CBMEM console.  Always accessed