[coreboot-gerrit] Patch set updated for coreboot: a898eec intel: Correct several MMIO related ACPI table settings
Dave Frodin (dave.frodin@se-eng.com)
gerrit at coreboot.org
Fri Apr 24 14:25:43 CEST 2015
Dave Frodin (dave.frodin at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9972
-gerrit
commit a898eec052da1e4a8c296c3688caab0222dea7b8
Author: Dave Frodin <dave.frodin at se-eng.com>
Date: Thu Apr 23 06:04:46 2015 -0600
intel: Correct several MMIO related ACPI table settings
1) The Rangeley chipset has the MMIO PCI config space feature
enabled at 0xe0000000-0xefffffff. This is a 256MB space
which covers all of config space. The ACPI table for
this space only defines it as being 64MB. This table
setting has been corrected in the rangeley.asl file.
2) Several of the intel platforms define the region reserved
for PCI memory resources in a location where it overlaps
with the MMIO (MCFG) region.
Using the memory map from mohon_peak as an example:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007fbcffff: RAM
4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES
5. 000000007fc00000-000000007fdfffff: RESERVED
6. 00000000e0000000-00000000efffffff: RESERVED
7. 00000000fee00000-00000000fee00fff: RESERVED
8. 0000000100000000-000000017fffffff: RAM
The ACPI table describing the space set aside for PCI memory
(not to be confused with the MMIO config space) is defined
as the region from BMBOUND (the top of DRAM below 4GB) to
a hardcoded value of 0xfebfffff. That region would overlap
the MMIO region at 0xe0000000-0xefffffff. For rangeley
the upper bound of the PCI memory space should be set
to 0xe0000000 - 1.
The MCFG regions for several of the affected chipsets are:
rangeley 0xe0000000-0xefffffff
baytrail 0xe0000000-0xefffffff
haswell 0xf0000000-0xf3ffffff
sandybridge 0xf8000000-0xfbffffff
TEST = intel/mohonpeak and intel/bayleybay.
Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90
Signed-off-by: Dave Frodin <dave.frodin at se-eng.com>
---
src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl | 8 ++++----
src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl | 2 +-
src/northbridge/intel/haswell/acpi/hostbridge.asl | 6 +++---
src/northbridge/intel/sandybridge/acpi/hostbridge.asl | 6 +++---
src/soc/intel/baytrail/acpi/southcluster.asl | 6 +++---
src/soc/intel/fsp_baytrail/acpi/southcluster.asl | 6 +++---
6 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
index 5cefaeb..4159c30 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
+++ b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
@@ -111,11 +111,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfebfffff)
+ // PCI Memory Region (Top of memory-0xdfffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0xfec00000,,, PM01)
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xe0000000,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -131,7 +131,7 @@ Method (_CRS, 0, Serialized)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
- Store (BMBD, PMIN) // Memory goes from BMBOUND to 0xfebfffff (PM01 above)
+ Store (BMBD, PMIN) // Memory goes from BMBOUND to 0xdfffffff (PM01 above)
Add(Subtract(PMAX, PMIN), 1, PLEN) // Store Memory Size
Return (MCRS)
diff --git a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
index 6a8c2e0..08dba89 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
+++ b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
@@ -30,7 +30,7 @@ Device (PDRC)
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x04000000)
+ Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000)
})
// Current Resource Settings
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 9bc5549..eb5aa76 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -426,11 +426,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfebfffff)
+ // PCI Memory Region (Top of memory-0xefffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0xfec00000,,, PM01)
+ 0x00000000, 0x00000000, 0xefffffff, 0x00000000,
+ 0xf0000000,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 26f7514..aba832c 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -344,11 +344,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfebfffff)
+ // PCI Memory Region (Top of memory-0xf7ffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0xfec00000,,, PM01)
+ 0x00000000, 0x00000000, 0xf7ffffff, 0x00000000,
+ 0xf8000000,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 47151a3..1385bd5 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -158,11 +158,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfeafffff)
+ // PCI Memory Region (Top of memory-0xdfffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
- 0x00100000,,, PMEM)
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xe0000000,,, PMEM)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
index 3ee9ee0..12e9daa 100644
--- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
@@ -157,11 +157,11 @@ Name (MCRS, ResourceTemplate()
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfeafffff)
+ // PCI Memory Region (Top of memory-0xdfffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
- 0x00100000,,, PMEM)
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xe0000000,,, PMEM)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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