[coreboot-gerrit] Patch merged into coreboot/master: 97ab425 rockchip/rk3288: Fix SPI clock divisor calculation

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 97ab4250e778d195eba8874f3e9bcbdc830f4dbc
Author: Julius Werner <jwerner at chromium.org>
Date:   Tue Mar 24 16:12:08 2015 -0700

    rockchip/rk3288: Fix SPI clock divisor calculation
    
    The code to calculate the RK3288 SPI controller's internal clock divisor
    is wrong: it assumes that the divisor register was an "n-1" divisor when
    it actually isn't (due to some misleading kernel code that was copied in
    here). This means that all SPI clocks are currently running lower than
    expected.
    
    This patch fixes the calculation and changes all callers such that the
    effective speeds stay the same.
    
    BRANCH=veyron
    BUG=chrome-os-partner:38352
    TEST=Booted Jerry with and without the patch, dumping the divisor for
    flash and EC clocks. Made sure it stays the same.
    
    Change-Id: I2336e2b81c2384b5076175fcf32717a3ab2ba0c5
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 1fd5b990f937019a9bee7bd693c91d6e2fca1adb
    Original-Change-Id: I094d57a5933c8b849f5c66194e6cc2952ab68b90
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/262269
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Reviewed-on: http://review.coreboot.org/9887
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9887 for details.

-gerrit