[coreboot-gerrit] Patch set updated for coreboot: c7113e8 rockchip/rk3288: Fix SPI clock divisor calculation
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Apr 21 11:19:30 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9887
-gerrit
commit c7113e825529d207e1c73ae3107a738515d4b733
Author: Julius Werner <jwerner at chromium.org>
Date: Tue Mar 24 16:12:08 2015 -0700
rockchip/rk3288: Fix SPI clock divisor calculation
The code to calculate the RK3288 SPI controller's internal clock divisor
is wrong: it assumes that the divisor register was an "n-1" divisor when
it actually isn't (due to some misleading kernel code that was copied in
here). This means that all SPI clocks are currently running lower than
expected.
This patch fixes the calculation and changes all callers such that the
effective speeds stay the same.
BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted Jerry with and without the patch, dumping the divisor for
flash and EC clocks. Made sure it stays the same.
Change-Id: I2336e2b81c2384b5076175fcf32717a3ab2ba0c5
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 1fd5b990f937019a9bee7bd693c91d6e2fca1adb
Original-Change-Id: I094d57a5933c8b849f5c66194e6cc2952ab68b90
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262269
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
src/mainboard/google/veyron_brain/bootblock.c | 2 +-
src/mainboard/google/veyron_danger/bootblock.c | 2 +-
src/mainboard/google/veyron_jerry/bootblock.c | 4 ++--
src/mainboard/google/veyron_mighty/bootblock.c | 4 ++--
src/mainboard/google/veyron_pinky/bootblock.c | 4 ++--
src/mainboard/google/veyron_rialto/bootblock.c | 2 +-
src/mainboard/google/veyron_speedy/bootblock.c | 4 ++--
src/soc/rockchip/rk3288/spi.c | 8 ++------
8 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
index 678059f..1586010 100644
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ b/src/mainboard/google/veyron_brain/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c
index 678059f..1586010 100644
--- a/src/mainboard/google/veyron_danger/bootblock.c
+++ b/src/mainboard/google/veyron_danger/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 985152b..43af3f5 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
+ rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 985152b..43af3f5 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
+ rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 985152b..43af3f5 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
+ rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index 135aece..f59f8e9 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 985152b..43af3f5 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
+ rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}
diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c
index aa70f3e..a8d2be3 100644
--- a/src/soc/rockchip/rk3288/spi.c
+++ b/src/soc/rockchip/rk3288/spi.c
@@ -94,12 +94,8 @@ static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable)
static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
{
- unsigned short clk_div = 0;
-
- /* Calculate clock divisor. */
- clk_div = SPI_SRCCLK_HZ / hz;
- clk_div = (clk_div + 1) & 0xfffe;
- assert((clk_div - 1) * hz == SPI_SRCCLK_HZ);
+ unsigned short clk_div = SPI_SRCCLK_HZ / hz;
+ assert(clk_div * hz == SPI_SRCCLK_HZ && !(clk_div & 1));
write32(®s->baudr, clk_div);
}
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