[coreboot-gerrit] Patch set updated for coreboot: 8ab91ab google/urara: use board ID information to set up hardware
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Apr 21 11:18:10 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9888
-gerrit
commit 8ab91abf1f3628a808e5e458998d668c5c5bcee3
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Mon Mar 9 15:31:38 2015 +0000
google/urara: use board ID information to set up hardware
The hardware initialization is now split in basic
initialization (MIPS and system PLL, system clock,
SPIM, UART), and initialization of other hardware
blocks (USB, I2C, ETH). The second part uses board ID
information to select setup that is board specific
(currently only I2C interface is selected through
board ID).
BRANCH=none
BUG=chrome-os-partner:37593
TEST=tested on bring up board for both Urara and Concerto;
to simulate the use of Concerto (I2C3) DIP SW17 was
set to 0.
it works with default settings on Urara
Change-Id: Ic5bbf28ab42545a4fb2aa6fd30592a02ecc15cb5
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: f2b3db2e7f9fa898214f974ca34ea427196d2e4e
Original-Change-Id: Iac9a082ad84444af1d9d9785a2d0cc3205140d15
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/257401
Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb at chromium.org>
---
src/arch/mips/bootblock_simple.c | 10 ++++-
src/include/boardid.h | 5 +++
src/mainboard/google/urara/Makefile.inc | 1 +
src/mainboard/google/urara/boardid.c | 26 ++++++++---
src/mainboard/google/urara/bootblock.c | 77 +++++++++++++++++++--------------
5 files changed, 80 insertions(+), 39 deletions(-)
diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c
index 64bbae2..85f9336 100644
--- a/src/arch/mips/bootblock_simple.c
+++ b/src/arch/mips/bootblock_simple.c
@@ -21,11 +21,14 @@
#include <bootblock_common.h>
#include <console/console.h>
+#include <halt.h>
#include <program_loading.h>
void main(void)
{
bootblock_cpu_init();
+
+ /* Mainboard basic init */
bootblock_mainboard_init();
#if CONFIG_BOOTBLOCK_CONSOLE
@@ -34,5 +37,10 @@ void main(void)
bootblock_mmu_init();
- run_romstage();
+ if (init_extra_hardware()) {
+ printk(BIOS_ERR, "bootblock_simple: failed to init HW.\n");
+ } else {
+ run_romstage();
+ }
+ halt();
}
diff --git a/src/include/boardid.h b/src/include/boardid.h
index 41c21d6..ce8dc6c 100644
--- a/src/include/boardid.h
+++ b/src/include/boardid.h
@@ -22,6 +22,11 @@
#include <stdint.h>
+struct board_hw {
+ uint8_t i2c_interface;
+};
+
+const struct board_hw *board_get_hw(void);
uint8_t board_id(void);
uint32_t ram_code(void);
diff --git a/src/mainboard/google/urara/Makefile.inc b/src/mainboard/google/urara/Makefile.inc
index 1428912..62dc3e4 100644
--- a/src/mainboard/google/urara/Makefile.inc
+++ b/src/mainboard/google/urara/Makefile.inc
@@ -19,6 +19,7 @@
# MA 02110-1301 USA
#
+bootblock-y += boardid.c
ramstage-y += boardid.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c
index 02cfa05..a95bc14 100644
--- a/src/mainboard/google/urara/boardid.c
+++ b/src/mainboard/google/urara/boardid.c
@@ -34,13 +34,14 @@
const struct bid_map {
const char *board_name;
uint8_t board_id;
+ struct board_hw hardware;
} board_id_map[] = {
- {"urara", URARA_BOARD_ID_BUB},
- {"buranku", URARA_BOARD_ID_BURANKU},
- {"derwent", URARA_BOARD_ID_DERWENT},
- {"jaguar", URARA_BOARD_ID_JAGUAR},
- {"kennet", URARA_BOARD_ID_KENNET},
- {"space", URARA_BOARD_ID_SPACE},
+ {"urara", URARA_BOARD_ID_BUB, {0} },
+ {"buranku", URARA_BOARD_ID_BURANKU, {3} },
+ {"derwent", URARA_BOARD_ID_DERWENT, {3} },
+ {"jaguar", URARA_BOARD_ID_JAGUAR, {3} },
+ {"kennet", URARA_BOARD_ID_KENNET, {3} },
+ {"space", URARA_BOARD_ID_SPACE, {3} },
};
static int cached_board_id = -1;
@@ -91,6 +92,19 @@ static uint8_t retrieve_board_id(void)
return 0;
}
+const struct board_hw *board_get_hw(void)
+{
+ int i;
+ uint8_t bid = board_id();
+
+ for (i = 0; i < ARRAY_SIZE(board_id_map); i++) {
+ if (bid == board_id_map[i].board_id)
+ return &(board_id_map[i].hardware);
+ }
+
+ return 0;
+}
+
uint8_t board_id(void)
{
if (cached_board_id == -1)
diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c
index 4530c8c..3692802 100644
--- a/src/mainboard/google/urara/bootblock.c
+++ b/src/mainboard/google/urara/bootblock.c
@@ -23,6 +23,7 @@
#include <stdint.h>
#include <soc/clocks.h>
#include <assert.h>
+#include <boardid.h>
#define PADS_FUNCTION_SELECT0_ADDR (0xB8101C00 + 0xC0)
@@ -172,15 +173,10 @@ static void i2c_mfio_setup(int interface)
write32(PADS_FUNCTION_SELECT0_ADDR, reg);
}
-static int init_clocks(void)
+static void bootblock_mainboard_init(void)
{
int ret;
- /*
- * Set up dividers for peripherals before setting up PLLs
- * in order to not over-clock them when enabling PLLs
- */
-
/* System PLL divided by 2 -> 400 MHz */
/* The same frequency will be the input frequency for the SPFI block */
system_clk_setup(1);
@@ -190,40 +186,57 @@ static int init_clocks(void)
* the values set or not by the boot ROM code */
mips_clk_setup(0, 0);
- /* System clock divided by 8 -> 50 MHz */
- ret = usb_clk_setup(7, 2, 7);
- if (ret != CLOCKS_OK)
- return ret;
-
- /* System PLL divided by 7 divided by 62 -> 1.8433 Mhz */
- uart1_clk_setup(6, 61);
-
- /* System PLL divided by 4 divided by 3 -> 33.33 MHz */
- i2c_clk_setup(3, 2, 0);
- /* Ethernet clocks setup: ENET as clock source */
- eth_clk_setup(0, 7);
-
- /* ROM clock setup: system clock divided by 2 -> 200 MHz */
- /* Hash accelerator is driven from the ROM clock */
- rom_clk_setup(1);
-
/* Setup system PLL at 800 MHz */
ret = sys_pll_setup(2, 1);
if (ret != CLOCKS_OK)
- return ret;
+ return;
/* Setup MIPS PLL at 546 MHz */
ret = mips_pll_setup(2, 1, 1, 21);
if (ret != CLOCKS_OK)
- return ret;
- return CLOCKS_OK;
+ return;
+
+ /* Setup SPIM1 MFIOs */
+ spim1_mfio_setup();
+ /* Setup UART1 clock and MFIOs
+ * System PLL divided by 7 divided by 62 -> 1.8433 Mhz
+ */
+ uart1_clk_setup(6, 61);
+ uart1_mfio_setup();
}
-static void bootblock_mainboard_init(void)
+
+static int init_extra_hardware(void)
{
- if (!init_clocks()) {
- /* Disable GPIO on the peripheral lines */
- uart1_mfio_setup();
- spim1_mfio_setup();
- i2c_mfio_setup(0);
+ const struct board_hw *hardware;
+
+ /* Obtain information about current board */
+ hardware = board_get_hw();
+ if (!hardware) {
+ printk(BIOS_ERR, "%s: Invalid hardware information.\n",
+ __func__);
+ return -1;
}
+
+ /* Setup USB clock
+ * System clock divided by 8 -> 50 MHz
+ */
+ if (usb_clk_setup(7, 2, 7) != CLOCKS_OK) {
+ printk(BIOS_ERR, "%s: Failed to set up USB clock.\n",
+ __func__);
+ return -1;
+ }
+
+ /* Setup I2C clocks and MFIOs
+ * System PLL divided by 4 divided by 3 -> 33.33 MHz
+ */
+ i2c_clk_setup(3, 2, hardware->i2c_interface);
+ i2c_mfio_setup(hardware->i2c_interface);
+
+ /* Ethernet clocks setup: ENET as clock source */
+ eth_clk_setup(0, 7);
+ /* ROM clock setup: system clock divided by 2 -> 200 MHz */
+ /* Hash accelerator is driven from the ROM clock */
+ rom_clk_setup(1);
+
+ return 0;
}
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