[coreboot-gerrit] Patch set updated for coreboot: 2221b8e imgtec/pistachio: increase RAM CBFS cache size

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9894

-gerrit

commit 2221b8ed79cba897f96dd4dbe3bebe6118af6a1a
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Mar 31 11:47:16 2015 -0700

    imgtec/pistachio: increase RAM CBFS cache size
    
    CBFS cache use is very close to the limit, does not allow to read much
    more from CBFS.
    
    BRANCH=none
    BUG=chrome-os-partner:36586
    TEST=the upcoming patches do not fail due to the lack of room in CBFS
         cache any more
    
    Change-Id: I8e784891e59ca284b3bd82557c2114a2f450d8a3
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c94d55c8042db81c1eb0c10d5f24883e00cdc19a
    Original-Change-Id: Ic09dbd5b4a0e165ccef396ff8a9e21b12c49b705
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/263268
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 802592f..c7ea04b 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -30,8 +30,8 @@ SECTIONS
 	DRAM_START(0x00000000)
 	/* DMA coherent area: accessed via KSEG1. */
 	DMA_COHERENT(0x00100000, 1M)
-	POSTRAM_CBFS_CACHE(0x00200000, 128K)
-	RAMSTAGE(0x00220000, 128K)
+	POSTRAM_CBFS_CACHE(0x00200000, 192K)
+	RAMSTAGE(0x00230000, 128K)
 
 	/*
 	 * GRAM becomes the SRAM.  Accessed through KSEG0 in the bootblock