[coreboot-gerrit] New patch to review for coreboot: a3dc793 google/veyron_*: Increase SPI flash frequency to 24.75MHz

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9889

-gerrit

commit a3dc793feb8c16df4025fdbdf907303a530815f8
Author: Julius Werner <jwerner at chromium.org>
Date:   Tue Mar 24 16:54:38 2015 -0700

    google/veyron_*: Increase SPI flash frequency to 24.75MHz
    
    This patch increases the SPI clock for the ROM to 24.75MHz on all rk3288
    (veyron) boards. This increases flash read speeds (and thereby decreases
    boot time) significantly, but we don't seem to get any more increases by
    going even higher. We have also seen occasional read failures at higher
    speeds in certain configurations, so this frequency seems to be the best
    option.
    
    BRANCH=veyron
    BUG=chrome-os-partner:38352
    TEST=Booted on Jerry with Servo attached.
    
    Change-Id: I9bdb62eff169fe2be33558caafe9891668589372
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a1d07da4266f2922b076dfae8396c24c6a84252b
    Original-Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/262645
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/mainboard/google/veyron_brain/bootblock.c  | 2 +-
 src/mainboard/google/veyron_danger/bootblock.c | 2 +-
 src/mainboard/google/veyron_jerry/bootblock.c  | 2 +-
 src/mainboard/google/veyron_mighty/bootblock.c | 2 +-
 src/mainboard/google/veyron_pinky/bootblock.c  | 2 +-
 src/mainboard/google/veyron_rialto/bootblock.c | 2 +-
 src/mainboard/google/veyron_speedy/bootblock.c | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
index 1586010..72ea5b1 100644
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ b/src/mainboard/google/veyron_brain/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c
index 1586010..72ea5b1 100644
--- a/src/mainboard/google/veyron_danger/bootblock.c
+++ b/src/mainboard/google/veyron_danger/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 43af3f5..b5b21b6 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 43af3f5..b5b21b6 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 43af3f5..b5b21b6 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index f59f8e9..b47e2e2 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 43af3f5..b5b21b6 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);