[coreboot-gerrit] Patch merged into coreboot/master: c447f43 veyron: Sync up SDRAM configurations

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c447f43f94e03bdf6666bfb956e0614869ad0915
Author: Julius Werner <jwerner at chromium.org>
Date:   Wed Feb 18 18:00:07 2015 -0800

    veyron: Sync up SDRAM configurations
    
    This patch adds all SDRAM configurations currently in use for any Veyron
    board to all boards. In the future we might decide that we want to reuse
    known good memory from one board on another, and having all of these in
    there already might help us avoid a firmware rev. We can still
    differentiate them later if the need ever arises.
    
    Not touching Rialto since it already decided to go its own way and
    replace an existing RAM code with it's own 1GB configuration. Also
    adjusting the names of the recently added DDR3 4GB configs to fit the
    existing scheme.
    
    Includes changes from "veyron: The ODT function is disabled LPDDR3".
    
    BRANCH=veyron
    BUG=None
    TEST=Compiled all Veyron boards, booted on Jerry.
    
    Change-Id: I817efd4b467a5a9587475a82df207048173e7bd5
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 36d3fe138b154a16700e3c7adbb33834ff1c5284
    Original-Change-Id: I4d037967dcb5cbd6b2b82f347f6b19541559b61a
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/255665
    Reviewed-on: http://review.coreboot.org/9829
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/9829 for details.

-gerrit