[coreboot-gerrit] Patch set updated for coreboot: d4fbf06 southbridge/intel: add generic sata ssdt port generator

[Alexander Couzens (lynxis@fe80.eu)]

Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9708

-gerrit

commit d4fbf0692e4678cb8db7e6e102e9a9984430a3f9
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Thu Apr 16 02:03:26 2015 +0200

    southbridge/intel: add generic sata ssdt port generator
    
    intel_generate_sata_ssdt_ports() generates ports based on sata enable map
    
    Change-Id: Ie68e19c93f093d6c61634c4adfde484b88f28a77
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 src/southbridge/intel/common/sata.c | 61 +++++++++++++++++++++++++++++++++++++
 src/southbridge/intel/common/sata.h |  4 +++
 2 files changed, 65 insertions(+)

diff --git a/src/southbridge/intel/common/sata.c b/src/southbridge/intel/common/sata.c
new file mode 100644
index 0000000..33c6256
--- /dev/null
+++ b/src/southbridge/intel/common/sata.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2015 Alexander Couzens <lynxis at fe80.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include "sata.h"
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+
+/* e.g.
+ * intel_generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3);
+ * generates:
+ * Scope (\_SB.PCI0.SATA)
+ * {
+ *     Device (PRT0)
+ *     {
+ *         Name (_ADR, 0x0000FFFF)  // _ADR: Address
+ *     }
+ *
+ *     Device (PRT1)
+ *     {
+ *         Name (_ADR, 0x0001FFFF)  // _ADR: Address
+ *     }
+ * }
+ */
+void intel_generate_sata_ssdt_ports(const char *scope, uint8_t enable_map)
+{
+	int i;
+	int bit;
+	char port_name[4] = "PRT0";
+
+	acpigen_write_scope(scope);
+
+	/* generate a device for every enabled port */
+	for (i = 0; i < 8; i++) {
+		bit = 1 << i;
+		if (!(bit & enable_map))
+			continue;
+
+		port_name[3] = '0' + i;
+		acpigen_write_device(port_name);
+
+		acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000);
+		acpigen_pop_len(); /* close PRT%d */
+	}
+
+	acpigen_pop_len(); /* close scope */
+}
diff --git a/src/southbridge/intel/common/sata.h b/src/southbridge/intel/common/sata.h
new file mode 100644
index 0000000..c6fcb4a
--- /dev/null
+++ b/src/southbridge/intel/common/sata.h
@@ -0,0 +1,4 @@
+
+#include <stdint.h>
+
+void intel_generate_sata_ssdt_ports(const char *scope, uint8_t enable_map);