[coreboot-gerrit] Patch set updated for coreboot: 72ee12c pistachio: Remove 50% DDR bandwidth restriction

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9847

-gerrit

commit 72ee12c99ba420f45e7e50f6ac7afcb2f9d8b679
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Thu Mar 5 17:25:48 2015 +0000

    pistachio: Remove 50% DDR bandwidth restriction
    
    The existing DDR setup configures the burst length to be 8. However
    the DDR controller can only be given sufficient data per clock to
    satisfy a burst length of 4, hence the bursts are only half
    populated. This results in a 50% drop of efficiency.
    
    Fix this by configuring the burst size to 4.
    
    BUG=chrome-os-partner:31438, chrome-os-partner:37087
    TEST=tested on Pistachio bring up board -> DDR initialized
         properly and ramstage executed correctly
    BRANCH=none
    
    Change-Id: I761ba73a04688841ca39a370b7cb99b6e0b22964
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 0e590ab8387dbbccef45dc84d1eeafee2abc9e2e
    Original-Change-Id: I585385b65e330624ad70292349e50c6695eeeb6c
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/256305
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/soc/imgtec/pistachio/ddr2_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c
index 0943cfa..ad5cf88 100644
--- a/src/soc/imgtec/pistachio/ddr2_init.c
+++ b/src/soc/imgtec/pistachio/ddr2_init.c
@@ -119,7 +119,7 @@
 #define DDRPHY_BISTUDPR_OFFSET		(0x0120)
 #define DDRPHY_DLLGCR_OFFSET		(0x0010)
 
-#define BL8		1
+#define BL8				0
 
 #define DDR_TIMEOUT_VALUE_US		100000