[coreboot-gerrit] New patch to review for coreboot: a49bb66 broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9814

-gerrit

commit a49bb66b1143d7c6a273bb1e85f2cd8822963c6b
Author: Todd Broch <tbroch at chromium.org>
Date:   Fri Feb 6 17:13:53 2015 -0800

    broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.
    
    Found that any non-USB3.0 devices connected to type-C ports
    (displayPort dongles) cause XHCI port to see connection which in turn
    leads us to enter USB compliance mode.
    
    That in turn causes the port to wake the system for a yet-to-be
    determined reason.  Clearing the PORTSC status bits (actually just
    CSC) seems to remedy the wake.
    
    Signed-off-by: Todd Broch <tbroch at chromium.org>
    
    BRANCH=samus
    BUG=chrome-os-partner:35320
    TEST=manual,
    
    1. Plug hoho into type-C port on samus and remove
    2. powerd_dbus_suspend
    
    Device stays asleep.
    
    Change-Id: Id3a291579ffca0152a7ef32e37ecae80ca08a82b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 0be5cba4916681dceb0372e76d9643e6c7175db5
    Original-Change-Id: I1396b9f8013dbbb31286c1d8958af592b3da7475
    Original-Reviewed-on: https://chromium-review.googlesource.com/247410
    Original-Commit-Queue: Todd Broch <tbroch at chromium.org>
    Original-Tested-by: Todd Broch <tbroch at chromium.org>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/broadwell/xhci.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index cfd0c56..9d0390e 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -179,6 +179,15 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
 		reg32 = read32(mem_base + 0x80e0);
 		reg32 |= (1 << 15);
 		write32(mem_base + 0x80e0, reg32);
+	} else {
+		/*
+		 * Clear port change status bits.  Clearing CSC alone seemed to
+		 * fix wakeup from S3 if entering USB compliance state even if
+		 * bit wasn't set on the port.
+		 */
+		int port;
+		for (port = 0; port < usb_xhci_port_count_usb3(dev); port++)
+			usb_xhci_reset_status_usb3(mem_base, port);
 	}
 
 	reg32 = read32(mem_base + 0x8154);