[coreboot-gerrit] Patch set updated for coreboot: 92a9d83 gigabyte/ga-b75m-d3v: Add GIGABYTE GA-B75M-D3V mainboard.
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Mon Apr 20 00:47:57 CEST 2015
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9803
-gerrit
commit 92a9d833e3ec00504bc8e34facb581a9c58ead00
Author: Damien Zammit <damien at zamaudio.com>
Date: Sun Apr 19 17:44:39 2015 +1000
gigabyte/ga-b75m-d3v: Add GIGABYTE GA-B75M-D3V mainboard.
Add option to fix firmware bug with r8168 network card
- Card reported to PCI allocator that memory was prefetchable
Remaining issues:
- VGA does not work with rom and there is no native VGA init.
- Currently need to disable coreboot's gma driver to prevent a hang.
- PCI allocator still has a bug (?) See boot log
Change-Id: I96b73a90c3d88672f0d238f4b735cd2f96ef99bd
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/device/device.c | 8 +-
src/device/pci_device.c | 141 ++++
src/drivers/net/Kconfig | 5 +
src/drivers/net/Makefile.inc | 1 +
src/drivers/net/realtek.c | 29 +
src/include/device/pci.h | 2 +
src/mainboard/gigabyte/ga-b75m-d3v/Kconfig | 75 ++
src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name | 2 +
src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc | 21 +
src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl | 0
.../gigabyte/ga-b75m-d3v/acpi/mainboard.asl | 49 ++
.../gigabyte/ga-b75m-d3v/acpi/platform.asl | 73 ++
.../gigabyte/ga-b75m-d3v/acpi/superio.asl | 24 +
.../gigabyte/ga-b75m-d3v/acpi/thermal.asl | 65 ++
src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl | 1 +
src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c | 83 ++
src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt | 6 +
src/mainboard/gigabyte/ga-b75m-d3v/boot.log | 833 +++++++++++++++++++++
src/mainboard/gigabyte/ga-b75m-d3v/cmos.default | 9 +
src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout | 130 ++++
src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb | 116 +++
src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl | 25 +
src/mainboard/gigabyte/ga-b75m-d3v/gpio.c | 433 +++++++++++
src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c | 8 +
src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c | 106 +++
src/mainboard/gigabyte/ga-b75m-d3v/mainboard_smi.c | 94 +++
src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 211 ++++++
src/mainboard/gigabyte/ga-b75m-d3v/thermal.h | 30 +
src/southbridge/intel/bd82x6x/lpc.c | 2 +-
29 files changed, 2577 insertions(+), 5 deletions(-)
diff --git a/src/device/device.c b/src/device/device.c
index b3b8d24..0c2498b 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -704,8 +704,8 @@ static void avoid_fixed_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next) {
if ((res->flags & IORESOURCE_FIXED))
continue;
- printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__,
- dev_path(dev), res->index, res->limit);
+ printk(BIOS_SPEW, "%s: %s@%08llx limit %08llx\n", __func__,
+ dev_path(dev), res->base, res->limit);
if ((res->flags & MEM_MASK) == PREF_TYPE &&
(res->limit < limits.pref.limit))
limits.pref.limit = res->limit;
@@ -737,8 +737,8 @@ static void avoid_fixed_resources(struct device *dev)
else
continue;
- printk(BIOS_SPEW, "%s2: %s@%02lx limit %08llx\n", __func__,
- dev_path(dev), res->index, res->limit);
+ printk(BIOS_SPEW, "%s2: %s@%08llx limit %08llx\n", __func__,
+ dev_path(dev), res->base, res->limit);
printk(BIOS_SPEW, "\tlim->base %08llx lim->limit %08llx\n",
lim->base, lim->limit);
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 4651258..74cc63f 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -163,6 +163,120 @@ unsigned pci_find_capability(device_t dev, unsigned cap)
/**
* Given a device and register, read the size of the BAR for that register.
+ * Hardcode any prefetch mem flags to mem (call only for buggy devices).
+ *
+ * @param dev Pointer to the device structure.
+ * @param index Address of the PCI configuration register.
+ * @return TODO
+ */
+struct resource *pci_get_resource_no_prefetch_mem(struct device *dev, unsigned long index)
+{
+ struct resource *resource;
+ unsigned long value, attr;
+ resource_t moving, limit;
+
+ /* Initialize the resources to nothing. */
+ resource = new_resource(dev, index);
+
+ /* Get the initial value. */
+ value = pci_read_config32(dev, index);
+
+ /* See which bits move. */
+ moving = pci_moving_config32(dev, index);
+
+ /* Initialize attr to the bits that do not move. */
+ attr = value & ~moving;
+
+ /* If it is a 64bit resource look at the high half as well. */
+ if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
+ ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
+ PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
+ /* Find the high bits that move. */
+ moving |=
+ ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
+ }
+
+ /* Find the resource constraints.
+ * Start by finding the bits that move. From there:
+ * - Size is the least significant bit of the bits that move.
+ * - Limit is all of the bits that move plus all of the lower bits.
+ * See PCI Spec 6.2.5.1.
+ */
+ limit = 0;
+ if (moving) {
+ resource->size = 1;
+ resource->align = resource->gran = 0;
+ while (!(moving & resource->size)) {
+ resource->size <<= 1;
+ resource->align += 1;
+ resource->gran += 1;
+ }
+ resource->limit = limit = moving | (resource->size - 1);
+ }
+
+ /*
+ * Some broken hardware has read-only registers that do not
+ * really size correctly.
+ *
+ * Example: the Acer M7229 has BARs 1-4 normally read-only,
+ * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
+ * by writing 0xffffffff to it, it will read back as 0x1f1 -- which
+ * is a violation of the spec.
+ *
+ * We catch this case and ignore it by observing which bits move.
+ *
+ * This also catches the common case of unimplemented registers
+ * that always read back as 0.
+ */
+ if (moving == 0) {
+ if (value != 0) {
+ printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
+ "read-only ignoring it\n",
+ dev_path(dev), index, value);
+ }
+ resource->flags = 0;
+ } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
+ /* An I/O mapped base address. */
+ attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
+ resource->flags |= IORESOURCE_IO;
+ /* I don't want to deal with 32bit I/O resources. */
+ resource->limit = 0xffff;
+ } else {
+ /* A Memory mapped base address. */
+ attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+ resource->flags |= IORESOURCE_MEM;
+ // Ignore prefetch
+ //if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH)
+ // resource->flags |= IORESOURCE_PREFETCH;
+ attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
+ if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
+ /* 32bit limit. */
+ resource->limit = 0xffffffffUL;
+ } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
+ /* 1MB limit. */
+ resource->limit = 0x000fffffUL;
+ } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
+ /* 64bit limit. */
+ resource->limit = 0xffffffffffffffffULL;
+ resource->flags |= IORESOURCE_PCI64;
+ } else {
+ /* Invalid value. */
+ printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
+ printk(BIOS_ERR, " on dev %s at index %02lx\n",
+ dev_path(dev), index);
+ resource->flags = 0;
+ }
+ }
+
+ /* Don't let the limit exceed which bits can move. */
+ if (resource->limit > limit)
+ resource->limit = limit;
+
+ return resource;
+}
+
+/**
+ * Given a device and register, read the size of the BAR for that register.
*
* @param dev Pointer to the device structure.
* @param index Address of the PCI configuration register.
@@ -325,6 +439,27 @@ static void pci_get_rom_resource(struct device *dev, unsigned long index)
}
/**
+ * Read the base address registers for a given device,
+ * but choose mem over prefetch mem for buggy devices.
+ *
+ * @param dev Pointer to the dev structure.
+ * @param howmany How many registers to read (6 for device, 2 for bridge).
+ */
+static void pci_read_bases_no_prefetch_mem(struct device *dev, unsigned int howmany)
+{
+ unsigned long index;
+
+ for (index = PCI_BASE_ADDRESS_0;
+ (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
+ struct resource *resource;
+ resource = pci_get_resource_no_prefetch_mem(dev, index);
+ index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
+ }
+
+ compact_resources(dev);
+}
+
+/**
* Read the base address registers for a given device.
*
* @param dev Pointer to the dev structure.
@@ -425,6 +560,12 @@ void pci_dev_read_resources(struct device *dev)
pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
}
+void pci_dev_read_resources_no_prefetch(struct device *dev)
+{
+ pci_read_bases_no_prefetch_mem(dev, 6);
+ pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
+}
+
void pci_bus_read_resources(struct device *dev)
{
pci_bridge_read_bases(dev);
diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig
new file mode 100644
index 0000000..f1631fd
--- /dev/null
+++ b/src/drivers/net/Kconfig
@@ -0,0 +1,5 @@
+config REALTEK_8168_FIX
+ bool "Realtek 8168 fixup"
+ help
+ Select this when you have a buggy realtek 8168 card
+ that thinks its memory is prefetchable.
diff --git a/src/drivers/net/Makefile.inc b/src/drivers/net/Makefile.inc
index 9b3008d..f6fd803 100644
--- a/src/drivers/net/Makefile.inc
+++ b/src/drivers/net/Makefile.inc
@@ -1,2 +1,3 @@
romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
+ramstage-$(CONFIG_REALTEK_8168_FIX) += realtek.c
diff --git a/src/drivers/net/realtek.c b/src/drivers/net/realtek.c
new file mode 100644
index 0000000..78d55a7
--- /dev/null
+++ b/src/drivers/net/realtek.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This driver simply forces the 10ec:8168 device not to use prefetchable
+ * memory addresses on buggy hardware, which fixes an issue with the pci
+ * allocator
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <stdlib.h>
+#include <string.h>
+
+static struct device_operations r8168bug_ops = {
+ .read_resources = pci_dev_read_resources_no_prefetch,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver r8168bug_driver __pci_driver = {
+ .ops = &r8168bug_ops,
+ .vendor = 0x10ec,
+ .device = 0x8168,
+};
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 4e712f9..27b3327 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -63,6 +63,7 @@ extern struct pci_driver epci_drivers[];
extern struct device_operations default_pci_ops_dev;
extern struct device_operations default_pci_ops_bus;
+void pci_dev_read_resources_no_prefetch(device_t dev);
void pci_dev_read_resources(device_t dev);
void pci_bus_read_resources(device_t dev);
void pci_dev_set_resources(device_t dev);
@@ -79,6 +80,7 @@ uint8_t pci_moving_config8(struct device *dev, unsigned reg);
uint16_t pci_moving_config16(struct device *dev, unsigned reg);
uint32_t pci_moving_config32(struct device *dev, unsigned reg);
struct resource *pci_get_resource(struct device *dev, unsigned long index);
+struct resource *pci_get_resource_no_prefetch_mem(struct device *dev, unsigned long index);
void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device);
void pci_dev_init(struct device *dev);
unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev);
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
new file mode 100644
index 0000000..cffc7f0
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
@@ -0,0 +1,75 @@
+if BOARD_GIGABYTE_GA_B75M_D3V
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA1155
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
+ select SOUTHBRIDGE_INTEL_C216
+ select CPU_MICROCODE_CBFS_NONE
+ select SUPERIO_ITE_IT8728F
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
+ select INTEL_INT15
+ select VGA
+ select INTEL_EDID
+ select UDELAY_TSC
+ select SERIRQ_CONTINUOUS_MODE
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf8000000
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 25
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config MAINBOARD_DIR
+ string
+ default gigabyte/ga-b75m-d3v
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "GA-B75M-D3V"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_ID
+ string
+ default "8086,0102"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0102.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config IFD_BIOS_SECTION
+ string
+ default "0x00600000:0x007fffff"
+
+config IFD_ME_SECTION
+ string
+ default "0x00001000:0x004fffff"
+
+endif # BOARD_GIGABYTE_GA_B75M_D3V
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name
new file mode 100644
index 0000000..92f5744
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_GA_B75M_D3V
+ bool "GA-B75M-D3V"
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc
new file mode 100644
index 0000000..a2efadd
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+romstage-y += gpio.c
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
new file mode 100644
index 0000000..519c60a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Method (BRTN, 1, Serialized)
+{
+ If (LEqual (And (DID1, 0x0F00), 0x0400))
+ {
+ Notify (\_SB.PCI0.GFX0.DD01, Arg0)
+ }
+
+ If (LEqual (And (DID2, 0x0F00), 0x0400))
+ {
+ Notify (\_SB.PCI0.GFX0.DD02, Arg0)
+ }
+
+ If (LEqual (And (DID3, 0x0F00), 0x0400))
+ {
+ Notify (\_SB.PCI0.GFX0.DD03, Arg0)
+ }
+
+ If (LEqual (And (DID4, 0x0F00), 0x0400))
+ {
+ Notify (\_SB.PCI0.GFX0.DD04, Arg0)
+ }
+
+ If (LEqual (And (DID5, 0x0F00), 0x0400))
+ {
+ Notify (\_SB.PCI0.GFX0.DD05, Arg0)
+ }
+}
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl
new file mode 100644
index 0000000..1448aeb
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl
new file mode 100644
index 0000000..753fc29
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl
new file mode 100644
index 0000000..f71611a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x03)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 10 seconds
+ Name (_TSP, 100)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1)
+ {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl
new file mode 100644
index 0000000..f87af3c
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl
@@ -0,0 +1 @@
+// Blank
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
new file mode 100644
index 0000000..73b1c11
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ acpi_update_thermal_table(gnvs);
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt
new file mode 100644
index 0000000..65bdd22
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL:
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/boot.log b/src/mainboard/gigabyte/ga-b75m-d3v/boot.log
new file mode 100644
index 0000000..0e13fc8
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/boot.log
@@ -0,0 +1,833 @@
+
+
+coreboot-4.0-9313-g5f81c07-dirty Sun Apr 19 22:34:02 UTC 2015 romstage starting...
+Setting up static southbridge registers... done.
+Disabling Watchdog reboot... done.
+Setting up static northbridge registers... done.
+Initializing Graphics...
+Back from sandybridge_early_initialization()
+SMBus controller enabled.
+CPU id(206a7): Intel(R) Pentium(R) CPU G860 @ 3.00GHz
+AES NOT supported, TXT NOT supported, VT supported
+PCH type: B75, device id: 1e49, rev id 4
+Intel ME early init
+Intel ME firmware is ready
+ME: Requested 32MB UMA
+Starting native Platform init
+ Row addr bits : 16
+ Column addr bits : 10
+ Number of ranks : 2
+ DIMM Capacity : 8192 MB
+ CAS latencies : 6 7 8 9 10 11
+ tCKmin : 1.250 ns
+ tAAmin : 13.125 ns
+ tWRmin : 15.000 ns
+ tRCDmin : 13.125 ns
+ tRRDmin : 6.000 ns
+ tRPmin : 13.125 ns
+ tRASmin : 35.000 ns
+ tRCmin : 48.125 ns
+ tRFCmin : 260.000 ns
+ tWTRmin : 7.500 ns
+ tRTPmin : 7.500 ns
+ tFAWmin : 30.000 ns
+rankmap[0] = 0x3
+ PLL busy...done
+PLL didn't lock. Retrying at lower frequency
+ PLL busy...done
+MCU frequency is set at : 666 MHz
+Selected DRAM frequency: 666 MHz
+Minimum CAS latency : 9T
+Selected CAS latency : 9T
+Selected CWL latency : 7T
+Selected tRCD : 9T
+Selected tRP : 9T
+Selected tRAS : 24T
+Selected tWR : 10T
+Selected tFAW : 20T
+Selected tRRD : 4T
+Selected tRTP : 5T
+Selected tWTR : 5T
+Selected tRFC : 174T
+[c14] = 3000000
+[320c] = 4024000
+[d14] = 0
+[330c] = 4000
+[4000] = 187999
+[4004] = ca145454
+[400c] = a0690
+[4298] = 5aae1450
+[42a4] = 41f97200
+[4400] = 187999
+[4404] = ca145454
+[440c] = a0690
+[4698] = 5aae1450
+[46a4] = 41f97200
+Done dimm mapping
+PCI:[a0] = 0
+PCI:[a4] = 2
+PCI:[bc] = c2a00000
+PCI:[a8] = 3b600000
+PCI:[ac] = 2
+PCI:[b8] = c0000000
+PCI:[b0] = c0a00000
+PCI:[b4] = c0800000
+PCI:[7c] = 7f
+PCI:[70] = fe000000
+PCI:[74] = 1
+PCI:[78] = fe000c00
+Done memory map
+RCOMP...done
+COMP2 done
+COMP1 done
+FORCE RCOMP and wait 20us...done
+Done io registers
+Done jedec reset
+Done MRS commands
+High adjust 0:0000ffffffffffff
+High adjust 1:0000ffffffffffff
+High adjust 2:0000ffffffffffff
+High adjust 3:0000ffffffffffff
+High adjust 4:00000000ffffffff
+High adjust 5:00000000ffffffff
+High adjust 6:00000000ffffffff
+High adjust 7:00000000ffffffff
+High adjust 0:0000ffffffffffff
+High adjust 1:0000ffffffffffff
+High adjust 2:0000ffffffffffff
+High adjust 3:0000ffffffffffff
+High adjust 4:00000000ffffffff
+High adjust 5:00000000ffffffff
+High adjust 6:00000000ffffffff
+High adjust 7:00000000ffffffff
+t123: 1912, 9120, 500
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : NO
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Normal
+ME: Current Operation State : Bring up
+ME: Current Operation Mode : Normal
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Clean Moff->Mx wake
+ME: Progress Phase State : Waiting for DID BIOS message
+ME: FWS2: 0x101f012e
+ME: Bist in progress: 0x0
+ME: ICC Status : 0x3
+ME: Invoke MEBx : 0x1
+ME: CPU replaced : 0x0
+ME: MBP ready : 0x1
+ME: MFS failure : 0x0
+ME: Warm reset req : 0x0
+ME: CPU repl valid : 0x1
+ME: (Reserved) : 0x0
+ME: FW update req : 0x0
+ME: (Reserved) : 0x0
+ME: Current state : 0x1f
+ME: Current PM event: 0x0
+ME: Progress code : 0x1
+PASSED! Tell ME that DRAM is ready
+ME: FWS2: 0x1050012e
+ME: Bist in progress: 0x0
+ME: ICC Status : 0x3
+ME: Invoke MEBx : 0x1
+ME: CPU replaced : 0x0
+ME: MBP ready : 0x1
+ME: MFS failure : 0x0
+ME: Warm reset req : 0x0
+ME: CPU repl valid : 0x1
+ME: (Reserved) : 0x0
+ME: FW update req : 0x0
+ME: (Reserved) : 0x0
+ME: Current state : 0x50
+ME: Current PM event: 0x0
+ME: Progress code : 0x1
+ME: Requested BIOS Action: Continue to boot
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : NO
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Normal
+ME: Current Operation State : M0 with UMA
+ME: Current Operation Mode : Normal
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Clean Moff->Mx wake
+ME: Progress Phase State : M0 kernel load
+memcfg DDR3 clock 1333 MHz
+memcfg channel assignment: A: 0, B 1, C 2
+memcfg channel[0] config (00620020):
+ ECC inactive
+ enhanced interleave mode on
+ rank interleave on
+ DIMMA 8192 MB width x8 dual rank, selected
+ DIMMB 0 MB width x8 single rank
+memcfg channel[1] config (00000000):
+ ECC inactive
+ enhanced interleave mode off
+ rank interleave off
+ DIMMA 0 MB width x8 single rank, selected
+ DIMMB 0 MB width x8 single rank
+CBMEM: root @ bffff000 254 entries.
+Relocate MRC DATA from feffa7ac to bfffd000 (1040 bytes)
+Trying CBFS ramstage loader.
+CBFS: loading stage @ 0x100000 (320048 bytes), entry @ 0x100000
+CBMEM: recovering 4/254 entries from root @ bffff000
+Moving GDT to bfffb000...ok
+
+
+coreboot-4.0-9313-g5f81c07-dirty Sun Apr 19 22:34:02 UTC 2015 ramstage starting...
+Normal boot.
+BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 0
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 0
+PCI: 00:1c.2: enabled 0
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 1
+PCI: 00:1f.0: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 1
+PNP: 002e.3: enabled 1
+PNP: 002e.4: enabled 1
+PNP: 002e.5: enabled 1
+PNP: 002e.6: enabled 1
+PNP: 002e.7: enabled 1
+PNP: 002e.a: enabled 0
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.4: enabled 0
+PCI: 00:1f.5: enabled 0
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 00: enabled 1
+ APIC: acac: enabled 0
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:02.0: enabled 1
+ PCI: 00:14.0: enabled 1
+ PCI: 00:16.0: enabled 1
+ PCI: 00:16.1: enabled 0
+ PCI: 00:16.2: enabled 0
+ PCI: 00:16.3: enabled 0
+ PCI: 00:19.0: enabled 0
+ PCI: 00:1a.0: enabled 1
+ PCI: 00:1b.0: enabled 1
+ PCI: 00:1c.0: enabled 1
+ PCI: 00:1c.1: enabled 0
+ PCI: 00:1c.2: enabled 0
+ PCI: 00:1c.3: enabled 0
+ PCI: 00:1c.4: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:1c.5: enabled 0
+ PCI: 00:1c.6: enabled 0
+ PCI: 00:1c.7: enabled 0
+ PCI: 00:1d.0: enabled 1
+ PCI: 00:1e.0: enabled 1
+ PCI: 00:1f.0: enabled 1
+ PNP: 002e.0: enabled 0
+ PNP: 002e.1: enabled 1
+ PNP: 002e.2: enabled 1
+ PNP: 002e.3: enabled 1
+ PNP: 002e.4: enabled 1
+ PNP: 002e.5: enabled 1
+ PNP: 002e.6: enabled 1
+ PNP: 002e.7: enabled 1
+ PNP: 002e.a: enabled 0
+ PCI: 00:1f.2: enabled 1
+ PCI: 00:1f.3: enabled 1
+ PCI: 00:1f.4: enabled 0
+ PCI: 00:1f.5: enabled 0
+scan_static_bus for Root Device
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [8086/0100] ops
+Normal boot.
+PCI: 00:00.0 [8086/0100] enabled
+PCI: Static device PCI: 00:01.0 not found, disabling it.
+PCI: 00:02.0 [8086/0000] ops
+PCI: 00:02.0 [8086/0102] enabled
+PCI: 00:14.0 [8086/0000] ops
+PCI: 00:14.0 [8086/1e31] enabled
+PCI: 00:16.0 [8086/1e3a] bus ops
+PCI: 00:16.0 [8086/1e3a] enabled
+PCI: 00:16.1: Disabling device
+PCI: 00:16.1 [8086/1e3b] disabled No operations
+PCI: 00:16.2: Disabling device
+PCI: 00:16.2 [8086/1e3c] disabled No operations
+PCI: 00:16.3: Disabling device
+PCI: 00:16.3 [8086/1e3d] disabled No operations
+PCI: 00:19.0: Disabling device
+PCI: 00:1a.0 [8086/0000] ops
+PCI: 00:1a.0 [8086/1e2d] enabled
+PCI: 00:1b.0 [8086/0000] ops
+PCI: 00:1b.0 [8086/1e20] enabled
+PCI: 00:1c.0 [8086/0000] bus ops
+PCI: 00:1c.0 [8086/1e10] enabled
+PCI: 00:1c.1: Disabling device
+PCI: 00:1c.2: Disabling device
+PCI: 00:1c.3: Disabling device
+PCI: 00:1c.4 [8086/0000] bus ops
+PCI: 00:1c.4 [8086/1e18] enabled
+PCI: 00:1c.5: Disabling device
+PCI: 00:1c.6: Disabling device
+PCI: 00:1c.7: Disabling device
+PCH: RPFN 0x76543210 -> 0xfed4ba90
+PCI: 00:1d.0 [8086/0000] ops
+PCI: 00:1d.0 [8086/1e26] enabled
+Capability: type 0x0d @ 0x50
+Capability: type 0x0d @ 0x50
+PCI: 00:1e.0 [8086/244e] enabled
+PCI: 00:1f.0 [8086/0000] bus ops
+PCI: 00:1f.0 [8086/1e49] enabled
+PCI: 00:1f.2 [8086/0000] ops
+PCI: 00:1f.2 [8086/1e00] enabled
+PCI: 00:1f.3 [8086/0000] bus ops
+PCI: 00:1f.3 [8086/1e22] enabled
+PCI: 00:1f.4: Disabling device
+PCI: 00:1f.5: Disabling device
+scan_static_bus for PCI: 00:16.0
+scan_static_bus for PCI: 00:16.0 done
+do_pci_scan_bridge for PCI: 00:1c.0
+PCI: pci_scan_bus for bus 01
+PCI: pci_scan_bus returning with max=001
+do_pci_scan_bridge returns max 1
+do_pci_scan_bridge for PCI: 00:1c.4
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [10ec/8168] ops
+PCI: 02:00.0 [10ec/8168] enabled
+PCI: pci_scan_bus returning with max=002
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+do_pci_scan_bridge returns max 2
+do_pci_scan_bridge for PCI: 00:1e.0
+PCI: pci_scan_bus for bus 03
+PCI: pci_scan_bus returning with max=003
+do_pci_scan_bridge returns max 3
+scan_static_bus for PCI: 00:1f.0
+PNP: 002e.0 disabled
+PNP: 002e.1 enabled
+PNP: 002e.2 enabled
+PNP: 002e.3 enabled
+PNP: 002e.4 enabled
+PNP: 002e.5 enabled
+PNP: 002e.6 enabled
+PNP: 002e.7 enabled
+PNP: 002e.a disabled
+scan_static_bus for PCI: 00:1f.0 done
+scan_static_bus for PCI: 00:1f.3
+scan_static_bus for PCI: 00:1f.3 done
+PCI: pci_scan_bus returning with max=003
+scan_static_bus for Root Device done
+done
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 422411 exit 0
+found VGA at PCI: 00:02.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+APIC: 00 missing read_resources
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000.
+PCI: 00:1c.0 read_resources bus 1 link: 0
+PCI: 00:1c.0 read_resources bus 1 link: 0 done
+PCI: 00:1c.4 read_resources bus 2 link: 0
+PCI: 00:1c.4 read_resources bus 2 link: 0 done
+PCI: 00:1e.0 read_resources bus 3 link: 0
+PCI: 00:1e.0 read_resources bus 3 link: 0 done
+PCI: 00:1f.0 read_resources bus 0 link: 0
+PCI: 00:1f.0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
+ PCI: 00:01.0
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
+ PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.0
+ PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:1c.1
+ PCI: 00:1c.2
+ PCI: 00:1c.3
+ PCI: 00:1c.4 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
+ PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:1f.0 child on link 0 PNP: 002e.0
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.0
+ PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.5
+ PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62
+ PNP: 002e.6
+ PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
+ PNP: 002e.a
+ PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:1f.3
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1f.4
+ PCI: 00:1f.5
+DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 02:00.0 10 * [0x0 - 0xff] io
+PCI: 00:1c.4 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.4 1c * [0x0 - 0xfff] io
+PCI: 00:02.0 20 * [0x1000 - 0x103f] io
+PCI: 00:1f.2 20 * [0x1040 - 0x105f] io
+PNP: 002e.4 60 * [0x1060 - 0x1067] io
+PNP: 002e.4 62 * [0x1068 - 0x106f] io
+PNP: 002e.7 62 * [0x1070 - 0x1077] io
+PNP: 002e.7 64 * [0x1078 - 0x107f] io
+PCI: 00:1f.2 10 * [0x1080 - 0x1087] io
+PCI: 00:1f.2 18 * [0x1088 - 0x108f] io
+PCI: 00:1f.2 14 * [0x1090 - 0x1093] io
+PCI: 00:1f.2 1c * [0x1094 - 0x1097] io
+PNP: 002e.5 60 * [0x1098 - 0x1098] io
+PNP: 002e.5 62 * [0x1099 - 0x1099] io
+PNP: 002e.7 60 * [0x109a - 0x109a] io
+DOMAIN: 0000 compute_resources_io: base: 109b size: 109b align: 12 gran: 0 limit: fff done
+DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 20 * [0x0 - 0x3fff] mem
+PCI: 02:00.0 18 * [0x4000 - 0x4fff] mem
+PCI: 00:1c.4 compute_resources_mem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
+PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem
+PCI: 00:1c.4 20 * [0x10400000 - 0x104fffff] mem
+PCI: 00:14.0 10 * [0x10500000 - 0x1050ffff] mem
+PCI: 00:1b.0 10 * [0x10510000 - 0x10513fff] mem
+PCI: 00:1f.2 24 * [0x10514000 - 0x105147ff] mem
+PCI: 00:1a.0 10 * [0x10514800 - 0x10514bff] mem
+PCI: 00:1d.0 10 * [0x10514c00 - 0x10514fff] mem
+PCI: 00:1f.3 10 * [0x10515000 - 0x105150ff] mem
+PCI: 00:16.0 10 * [0x10515100 - 0x1051510f] mem
+DOMAIN: 0000 compute_resources_mem: base: 10515110 size: 10515110 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources: DOMAIN: 0000 at 00000000 limit 00000fff
+avoid_fixed_resources: DOMAIN: 0000 at 00000000 limit ffffffff
+constrain_resources: DOMAIN: 0000
+constrain_resources: PCI: 00:00.0
+constrain_resources: PCI: 00:02.0
+constrain_resources: PCI: 00:14.0
+constrain_resources: PCI: 00:16.0
+constrain_resources: PCI: 00:1a.0
+constrain_resources: PCI: 00:1b.0
+constrain_resources: PCI: 00:1c.0
+constrain_resources: PCI: 00:1c.4
+constrain_resources: PCI: 02:00.0
+constrain_resources: PCI: 00:1d.0
+constrain_resources: PCI: 00:1e.0
+constrain_resources: PCI: 00:1f.0
+constrain_resources: PNP: 002e.1
+constrain_resources: PNP: 002e.2
+constrain_resources: PNP: 002e.3
+constrain_resources: PNP: 002e.4
+constrain_resources: PNP: 002e.5
+constrain_resources: PNP: 002e.6
+constrain_resources: PNP: 002e.7
+constrain_resources: PCI: 00:1f.2
+constrain_resources: PCI: 00:1f.3
+avoid_fixed_resources2: DOMAIN: 0000 at 00000000 limit 00000fff
+ lim->base 00000000 lim->limit 000002f7
+avoid_fixed_resources2: DOMAIN: 0000 at 00000000 limit ffffffff
+ lim->base 00000000 lim->limit f7ffffff
+Setting resources...
+DOMAIN: 0000 allocate_resources_io: base:0 size:109b align:12 gran:0 limit:2f7
+!! Resource didn't fit !!
+ aligned base 0 size 1000 limit 2f7
+ fff needs to be <= 2f7 (limit)
+ PCI: 00:1c.4 1c * [0x0 - 0xfff] io
+PCI: 00:1c.4 1c * [0x0 - 0xfff] io
+Assigned: PCI: 00:02.0 20 * [0x0 - 0x3f] io
+Assigned: PCI: 00:1f.2 20 * [0x40 - 0x5f] io
+Assigned: PNP: 002e.4 60 * [0x60 - 0x67] io
+Assigned: PNP: 002e.4 62 * [0x68 - 0x6f] io
+Assigned: PNP: 002e.7 62 * [0x70 - 0x77] io
+Assigned: PNP: 002e.7 64 * [0x78 - 0x7f] io
+Assigned: PCI: 00:1f.2 10 * [0x80 - 0x87] io
+Assigned: PCI: 00:1f.2 18 * [0x88 - 0x8f] io
+Assigned: PCI: 00:1f.2 14 * [0x90 - 0x93] io
+Assigned: PCI: 00:1f.2 1c * [0x94 - 0x97] io
+Assigned: PNP: 002e.5 60 * [0x98 - 0x98] io
+Assigned: PNP: 002e.5 62 * [0x99 - 0x99] io
+Assigned: PNP: 002e.7 60 * [0x9a - 0x9a] io
+DOMAIN: 0000 allocate_resources_io: next_base: 9b size: 109b align: 12 gran: 0 done
+PCI: 00:1c.0 allocate_resources_io: base:2f7 size:0 align:12 gran:12 limit:2f7
+PCI: 00:1c.0 allocate_resources_io: next_base: 2f7 size: 0 align: 12 gran: 12 done
+PCI: 00:1c.4 allocate_resources_io: base:0 size:1000 align:12 gran:12 limit:2f7
+Assigned: PCI: 02:00.0 10 * [0x0 - 0xff] io
+PCI: 00:1c.4 allocate_resources_io: next_base: 100 size: 1000 align: 12 gran: 12 done
+PCI: 00:1e.0 allocate_resources_io: base:2f7 size:0 align:12 gran:12 limit:2f7
+PCI: 00:1e.0 allocate_resources_io: next_base: 2f7 size: 0 align: 12 gran: 12 done
+DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10515110 align:28 gran:0 limit:f7ffffff
+Assigned: PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem
+Assigned: PCI: 00:02.0 10 * [0xf0000000 - 0xf03fffff] mem
+Assigned: PCI: 00:1c.4 20 * [0xf0400000 - 0xf04fffff] mem
+Assigned: PCI: 00:14.0 10 * [0xf0500000 - 0xf050ffff] mem
+Assigned: PCI: 00:1b.0 10 * [0xf0510000 - 0xf0513fff] mem
+Assigned: PCI: 00:1f.2 24 * [0xf0514000 - 0xf05147ff] mem
+Assigned: PCI: 00:1a.0 10 * [0xf0514800 - 0xf0514bff] mem
+Assigned: PCI: 00:1d.0 10 * [0xf0514c00 - 0xf0514fff] mem
+Assigned: PCI: 00:1f.3 10 * [0xf0515000 - 0xf05150ff] mem
+Assigned: PCI: 00:16.0 10 * [0xf0515100 - 0xf051510f] mem
+DOMAIN: 0000 allocate_resources_mem: next_base: f0515110 size: 10515110 align: 28 gran: 0 done
+PCI: 00:1c.0 allocate_resources_prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:1c.0 allocate_resources_prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 allocate_resources_mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:1c.0 allocate_resources_mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.4 allocate_resources_prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:1c.4 allocate_resources_prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.4 allocate_resources_mem: base:f0400000 size:100000 align:20 gran:20 limit:f7ffffff
+Assigned: PCI: 02:00.0 20 * [0xf0400000 - 0xf0403fff] mem
+Assigned: PCI: 02:00.0 18 * [0xf0404000 - 0xf0404fff] mem
+PCI: 00:1c.4 allocate_resources_mem: next_base: f0405000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1e.0 allocate_resources_prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:1e.0 allocate_resources_prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1e.0 allocate_resources_mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:1e.0 allocate_resources_mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+TOUUD 0x23b600000 TOLUD 0xc2a00000 TOM 0x200000000
+MEBASE 0x1fe000000
+IGD decoded, subtracting 32M UMA and 2M GTT
+TSEG base 0xc0000000 size 8M
+Available memory below 4GB: 3072M
+Available memory above 4GB: 5046M
+Adding PCIe config bar base=0xf8000000 size=0x4000000
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:00.0 cf <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem<mmconfig>
+PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f03fffff] size 0x00400000 gran 0x16 mem64
+PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:02.0 20 <- [0x0000000000 - 0x000000003f] size 0x00000040 gran 0x06 io
+PCI: 00:14.0 10 <- [0x00f0500000 - 0x00f050ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:16.0 10 <- [0x00f0515100 - 0x00f051510f] size 0x00000010 gran 0x04 mem64
+PCI: 00:1a.0 10 <- [0x00f0514800 - 0x00f0514bff] size 0x00000400 gran 0x0a mem
+PCI: 00:1b.0 10 <- [0x00f0510000 - 0x00f0513fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.0 1c <- [0x00000002f7 - 0x00000002f6] size 0x00000000 gran 0x0c bus 01 io
+PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem
+PCI: 00:1c.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem
+PCI: 00:1c.4 1c <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c bus 02 io
+PCI: 00:1c.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:1c.4 20 <- [0x00f0400000 - 0x00f04fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:1c.4 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x0000000000 - 0x00000000ff] size 0x00000100 gran 0x08 io
+PCI: 02:00.0 18 <- [0x00f0404000 - 0x00f0404fff] size 0x00001000 gran 0x0c mem64
+PCI: 02:00.0 20 <- [0x00f0400000 - 0x00f0403fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.4 assign_resources, bus 2 link: 0
+PCI: 00:1d.0 10 <- [0x00f0514c00 - 0x00f0514fff] size 0x00000400 gran 0x0a mem
+PCI: 00:1e.0 1c <- [0x00000002f7 - 0x00000002f6] size 0x00000000 gran 0x0c bus 03 io
+PCI: 00:1e.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 prefmem
+PCI: 00:1e.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 mem
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+PNP: 002e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
+PNP: 002e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
+PNP: 002e.3 60 <- [0x0000000378 - 0x000000037b] size 0x00000004 gran 0x02 io
+PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
+PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq
+PNP: 002e.4 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
+PNP: 002e.4 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io
+PNP: 002e.4 62 <- [0x0000000068 - 0x000000006f] size 0x00000008 gran 0x03 io
+PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
+PNP: 002e.5 60 <- [0x0000000098 - 0x0000000098] size 0x00000001 gran 0x00 io
+PNP: 002e.5 62 <- [0x0000000099 - 0x0000000099] size 0x00000001 gran 0x00 io
+PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
+PNP: 002e.7 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq
+PNP: 002e.7 60 <- [0x000000009a - 0x000000009a] size 0x00000001 gran 0x00 io
+PNP: 002e.7 62 <- [0x0000000070 - 0x0000000077] size 0x00000008 gran 0x03 io
+PNP: 002e.7 64 <- [0x0000000078 - 0x000000007f] size 0x00000008 gran 0x03 io
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PCI: 00:1f.2 10 <- [0x0000000080 - 0x0000000087] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 14 <- [0x0000000090 - 0x0000000093] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 18 <- [0x0000000088 - 0x000000008f] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 1c <- [0x0000000094 - 0x0000000097] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 20 <- [0x0000000040 - 0x000000005f] size 0x00000020 gran 0x05 io
+PCI: 00:1f.2 24 <- [0x00f0514000 - 0x00f05147ff] size 0x00000800 gran 0x0b mem
+PCI: 00:1f.3 10 <- [0x00f0515000 - 0x00f05150ff] size 0x00000100 gran 0x08 mem64
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 109b align 12 gran 0 limit 2f7 flags 40040100 index 10000000
+ DOMAIN: 0000 resource base e0000000 size 10515110 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
+ DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
+ DOMAIN: 0000 resource base 100000000 size 13b600000 align 0 gran 0 limit 0 flags e0004200 index 5
+ DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
+ DOMAIN: 0000 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
+ DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
+ DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
+ DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a
+ DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
+ PCI: 00:01.0
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base f0000000 size 400000 align 22 gran 22 limit f7ffffff flags 60000201 index 10
+ PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit f7ffffff flags 60001201 index 18
+ PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit 2f7 flags 60000100 index 20
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base f0500000 size 10000 align 16 gran 16 limit f7ffffff flags 60000201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base f0515100 size 10 align 4 gran 4 limit f7ffffff flags 60000201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base f0514800 size 400 align 10 gran 10 limit f7ffffff flags 60000200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base f0510000 size 4000 align 14 gran 14 limit f7ffffff flags 60000201 index 10
+ PCI: 00:1c.0
+ PCI: 00:1c.0 resource base 2f7 size 0 align 12 gran 12 limit 2f7 flags 60080102 index 1c
+ PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
+ PCI: 00:1c.1
+ PCI: 00:1c.2
+ PCI: 00:1c.3
+ PCI: 00:1c.4 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.4 resource base 0 size 1000 align 12 gran 12 limit 2f7 flags 60080102 index 1c
+ PCI: 00:1c.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:1c.4 resource base f0400000 size 100000 align 20 gran 20 limit f7ffffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit 2f7 flags 60000100 index 10
+ PCI: 02:00.0 resource base f0404000 size 1000 align 12 gran 12 limit f7ffffff flags 60000201 index 18
+ PCI: 02:00.0 resource base f0400000 size 4000 align 14 gran 14 limit f7ffffff flags 60000201 index 20
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base f0514c00 size 400 align 10 gran 10 limit f7ffffff flags 60000200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1e.0 resource base 2f7 size 0 align 12 gran 12 limit 2f7 flags 60080102 index 1c
+ PCI: 00:1e.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:1e.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
+ PCI: 00:1f.0 child on link 0 PNP: 002e.0
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.0
+ PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags e0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.4 resource base 60 size 8 align 3 gran 3 limit 2f7 flags 60000100 index 60
+ PNP: 002e.4 resource base 68 size 8 align 3 gran 3 limit 2f7 flags 60000100 index 62
+ PNP: 002e.5
+ PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.5 resource base 98 size 1 align 0 gran 0 limit 2f7 flags 60000100 index 60
+ PNP: 002e.5 resource base 99 size 1 align 0 gran 0 limit 2f7 flags 60000100 index 62
+ PNP: 002e.6
+ PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.7 resource base 9a size 1 align 0 gran 0 limit 2f7 flags 60000100 index 60
+ PNP: 002e.7 resource base 70 size 8 align 3 gran 3 limit 2f7 flags 60000100 index 62
+ PNP: 002e.7 resource base 78 size 8 align 3 gran 3 limit 2f7 flags 60000100 index 64
+ PNP: 002e.a
+ PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 80 size 8 align 3 gran 3 limit 2f7 flags 60000100 index 10
+ PCI: 00:1f.2 resource base 90 size 4 align 2 gran 2 limit 2f7 flags 60000100 index 14
+ PCI: 00:1f.2 resource base 88 size 8 align 3 gran 3 limit 2f7 flags 60000100 index 18
+ PCI: 00:1f.2 resource base 94 size 4 align 2 gran 2 limit 2f7 flags 60000100 index 1c
+ PCI: 00:1f.2 resource base 40 size 20 align 5 gran 5 limit 2f7 flags 60000100 index 20
+ PCI: 00:1f.2 resource base f0514000 size 800 align 11 gran 11 limit f7ffffff flags 60000200 index 24
+ PCI: 00:1f.3
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base f0515000 size 100 align 8 gran 8 limit f7ffffff flags 60000201 index 10
+ PCI: 00:1f.4
+ PCI: 00:1f.5
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 2272059 exit 0
+Enabling resources...
+PCI: 00:00.0 subsystem <- 1458/5000
+PCI: 00:00.0 cmd <- 06
+PCI: 00:02.0 subsystem <- 1458/d000
+PCI: 00:02.0 cmd <- 03
+PCI: 00:14.0 subsystem <- 1458/5007
+PCI: 00:14.0 cmd <- 102
+PCI: 00:16.0 subsystem <- 1458/5000
+PCI: 00:16.0 cmd <- 02
+PCI: 00:1a.0 subsystem <- 1458/5006
+PCI: 00:1a.0 cmd <- 102
+PCI: 00:1b.0 subsystem <- 1458/a002
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 1458/5000
+PCI: 00:1c.0 cmd <- 100
+PCI: 00:1c.4 bridge ctrl <- 0003
+PCI: 00:1c.4 subsystem <- 1458/5000
+PCI: 00:1c.4 cmd <- 107
+PCI: 00:1c.4 init 155 usecs
+PCI: 00:1d.0 init
+EHCI: Setting up controller.. done.
+PCI: 00:1d.0 init 4724 usecs
+PCI: 00:1f.0 init
+pch: lpc_init
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+IOAPIC: Dumping registers
+ reg 0x0000: 0x02000000
+ reg 0x0001: 0x00170020
+ reg 0x0002: 0x00170020
+Set power off after power failure.
+NMI sources disabled.
+PantherPoint PM init
+rtc_failed = 0x0
+RTC Init
+Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
+done.
+Locking SMM.
+PCI: 00:1f.0 init 37453 usecs
+PCI: 00:1f.2 init
+SATA: Initializing...
+SATA: Controller in AHCI mode.
+ABAR: f0514000
+PCI: 00:1f.2 init 7569 usecs
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default
new file mode 100644
index 0000000..21d75e5
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+last_boot=Fallback
+baud_rate=115200
+debug_level=Spew
+power_on_after_fail=Enable
+nmi=Enable
+volume=0x3
+sata_mode=AHCI
+hyper_threading=Enable
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout
new file mode 100644
index 0000000..ca70c71
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout
@@ -0,0 +1,130 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+400 8 h 0 volume
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+#411 10 r 0 unused
+421 1 e 9 sata_mode
+#422 2 r 0 unused
+
+# coreboot config options: cpu
+424 1 e 2 hyper_threading
+#425 7 r 0 unused
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+#435 549 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 IDE
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
new file mode 100644
index 0000000..1e75bce
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
@@ -0,0 +1,116 @@
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA1155
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ register "pstate_coord_type" = "0xfe"
+ register "c1_acpower" = "1"
+ register "c2_acpower" = "3"
+ register "c3_acpower" = "5"
+ register "c1_battery" = "1"
+ register "c2_battery" = "3"
+ register "c3_battery" = "5"
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1458 0x5000 inherit
+ device pci 00.0 on # host bridge
+ subsystemid 0x1458 0x5000
+ end
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on # vga controller
+ subsystemid 0x1458 0xd000
+ end
+
+ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+
+ # GPI routing
+ register "alt_gp_smi_en" = "0x0000"
+ register "gen1_dec" = "0x003c0a01"
+
+ # Set max SATA speed to 6.0 Gb/s
+ register "sata_port_map" = "0x3f"
+ register "sata_interface_speed_support" = "0x3"
+
+ register "pcie_port_coalesce" = "0"
+ register "p_cnt_throttling_supported" = "0"
+ register "docking_supported" = "0"
+ register "c2_latency" = "0x0065"
+
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x1458 0x5007
+ end
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x1458 0x5006
+ end
+ device pci 1b.0 on # High Definition Audio
+ subsystemid 0x1458 0xa002
+ end
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 on # PCIe Port #5
+ device pci 00.0 on # PCI 10ec:8168
+ subsystemid 0x1458 0xe000
+ end
+ end
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x1458 0x5006
+ end
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA/LPC bridge
+ subsystemid 0x1458 0x5001
+ chip superio/ite/it8728f
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 on # Serial Port 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # EC
+ irq 0x70 = 1
+ end
+ device pnp 2e.5 on # Keyboard
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ irq 0x70 = 0
+ end
+ device pnp 2e.a off end # IR
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x1458 0xb005
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1458 0x5001
+ end
+ device pci 1f.4 off end
+ device pci 1f.5 off end # SATA Controller 2
+ end
+ end
+end
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
new file mode 100644
index 0000000..1ce6dd4
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
@@ -0,0 +1,25 @@
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c
new file mode 100644
index 0000000..1f2c5e7
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c
@@ -0,0 +1,433 @@
+#include "southbridge/intel/bd82x6x/gpio.h"
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_NATIVE,
+ .gpio7 = GPIO_MODE_NATIVE,
+ .gpio8 = GPIO_MODE_NATIVE,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_NATIVE,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_NATIVE,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_NATIVE,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_NATIVE,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_NATIVE,
+ .gpio28 = GPIO_MODE_NATIVE,
+ .gpio29 = GPIO_MODE_NATIVE,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_OUTPUT,
+ .gpio2 = GPIO_DIR_OUTPUT,
+ .gpio3 = GPIO_DIR_OUTPUT,
+ .gpio4 = GPIO_DIR_OUTPUT,
+ .gpio5 = GPIO_DIR_OUTPUT,
+ .gpio6 = GPIO_DIR_OUTPUT,
+ .gpio7 = GPIO_DIR_OUTPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio11 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_OUTPUT,
+ .gpio14 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio30 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_HIGH,
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio2 = GPIO_LEVEL_HIGH,
+ .gpio3 = GPIO_LEVEL_HIGH,
+ .gpio4 = GPIO_LEVEL_HIGH,
+ .gpio5 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio7 = GPIO_LEVEL_HIGH,
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio11 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio13 = GPIO_LEVEL_HIGH,
+ .gpio14 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio16 = GPIO_LEVEL_HIGH,
+ .gpio17 = GPIO_LEVEL_LOW,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio19 = GPIO_LEVEL_LOW,
+ .gpio20 = GPIO_LEVEL_LOW,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+ .gpio30 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio0 = GPIO_RESET_PWROK,
+ .gpio1 = GPIO_RESET_PWROK,
+ .gpio2 = GPIO_RESET_PWROK,
+ .gpio3 = GPIO_RESET_PWROK,
+ .gpio4 = GPIO_RESET_PWROK,
+ .gpio5 = GPIO_RESET_PWROK,
+ .gpio6 = GPIO_RESET_PWROK,
+ .gpio7 = GPIO_RESET_PWROK,
+ .gpio8 = GPIO_RESET_PWROK,
+ .gpio9 = GPIO_RESET_PWROK,
+ .gpio10 = GPIO_RESET_PWROK,
+ .gpio11 = GPIO_RESET_PWROK,
+ .gpio12 = GPIO_RESET_PWROK,
+ .gpio13 = GPIO_RESET_PWROK,
+ .gpio14 = GPIO_RESET_PWROK,
+ .gpio15 = GPIO_RESET_PWROK,
+ .gpio16 = GPIO_RESET_PWROK,
+ .gpio17 = GPIO_RESET_PWROK,
+ .gpio18 = GPIO_RESET_PWROK,
+ .gpio19 = GPIO_RESET_PWROK,
+ .gpio20 = GPIO_RESET_PWROK,
+ .gpio21 = GPIO_RESET_PWROK,
+ .gpio22 = GPIO_RESET_PWROK,
+ .gpio23 = GPIO_RESET_PWROK,
+ .gpio24 = GPIO_RESET_RSMRST,
+ .gpio25 = GPIO_RESET_PWROK,
+ .gpio26 = GPIO_RESET_PWROK,
+ .gpio27 = GPIO_RESET_PWROK,
+ .gpio28 = GPIO_RESET_PWROK,
+ .gpio29 = GPIO_RESET_PWROK,
+ .gpio30 = GPIO_RESET_PWROK,
+ .gpio31 = GPIO_RESET_PWROK,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_NO_INVERT,
+ .gpio1 = GPIO_NO_INVERT,
+ .gpio2 = GPIO_NO_INVERT,
+ .gpio3 = GPIO_NO_INVERT,
+ .gpio4 = GPIO_NO_INVERT,
+ .gpio5 = GPIO_NO_INVERT,
+ .gpio6 = GPIO_NO_INVERT,
+ .gpio7 = GPIO_NO_INVERT,
+ .gpio8 = GPIO_NO_INVERT,
+ .gpio9 = GPIO_NO_INVERT,
+ .gpio10 = GPIO_NO_INVERT,
+ .gpio11 = GPIO_NO_INVERT,
+ .gpio12 = GPIO_NO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_NO_INVERT,
+ .gpio15 = GPIO_NO_INVERT,
+ .gpio16 = GPIO_NO_INVERT,
+ .gpio17 = GPIO_NO_INVERT,
+ .gpio18 = GPIO_NO_INVERT,
+ .gpio19 = GPIO_NO_INVERT,
+ .gpio20 = GPIO_NO_INVERT,
+ .gpio21 = GPIO_NO_INVERT,
+ .gpio22 = GPIO_NO_INVERT,
+ .gpio23 = GPIO_NO_INVERT,
+ .gpio24 = GPIO_NO_INVERT,
+ .gpio25 = GPIO_NO_INVERT,
+ .gpio26 = GPIO_NO_INVERT,
+ .gpio27 = GPIO_NO_INVERT,
+ .gpio28 = GPIO_NO_INVERT,
+ .gpio29 = GPIO_NO_INVERT,
+ .gpio30 = GPIO_NO_INVERT,
+ .gpio31 = GPIO_NO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+ .gpio0 = GPIO_NO_BLINK,
+ .gpio1 = GPIO_NO_BLINK,
+ .gpio2 = GPIO_NO_BLINK,
+ .gpio3 = GPIO_NO_BLINK,
+ .gpio4 = GPIO_NO_BLINK,
+ .gpio5 = GPIO_NO_BLINK,
+ .gpio6 = GPIO_NO_BLINK,
+ .gpio7 = GPIO_NO_BLINK,
+ .gpio8 = GPIO_NO_BLINK,
+ .gpio9 = GPIO_NO_BLINK,
+ .gpio10 = GPIO_NO_BLINK,
+ .gpio11 = GPIO_NO_BLINK,
+ .gpio12 = GPIO_NO_BLINK,
+ .gpio13 = GPIO_NO_BLINK,
+ .gpio14 = GPIO_NO_BLINK,
+ .gpio15 = GPIO_NO_BLINK,
+ .gpio16 = GPIO_NO_BLINK,
+ .gpio17 = GPIO_NO_BLINK,
+ .gpio18 = GPIO_BLINK,
+ .gpio19 = GPIO_NO_BLINK,
+ .gpio20 = GPIO_NO_BLINK,
+ .gpio21 = GPIO_NO_BLINK,
+ .gpio22 = GPIO_NO_BLINK,
+ .gpio23 = GPIO_NO_BLINK,
+ .gpio24 = GPIO_NO_BLINK,
+ .gpio25 = GPIO_NO_BLINK,
+ .gpio26 = GPIO_NO_BLINK,
+ .gpio27 = GPIO_NO_BLINK,
+ .gpio28 = GPIO_NO_BLINK,
+ .gpio29 = GPIO_NO_BLINK,
+ .gpio30 = GPIO_NO_BLINK,
+ .gpio31 = GPIO_NO_BLINK,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio58 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+ .gpio61 = GPIO_DIR_OUTPUT,
+ .gpio62 = GPIO_DIR_OUTPUT,
+ .gpio63 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_LOW,
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_HIGH,
+ .gpio40 = GPIO_LEVEL_HIGH,
+ .gpio41 = GPIO_LEVEL_HIGH,
+ .gpio42 = GPIO_LEVEL_HIGH,
+ .gpio43 = GPIO_LEVEL_HIGH,
+ .gpio44 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_HIGH,
+ .gpio46 = GPIO_LEVEL_HIGH,
+ .gpio47 = GPIO_LEVEL_LOW,
+ .gpio48 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_LOW,
+ .gpio54 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_LOW,
+ .gpio56 = GPIO_LEVEL_LOW,
+ .gpio57 = GPIO_LEVEL_HIGH,
+ .gpio58 = GPIO_LEVEL_HIGH,
+ .gpio59 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+ .gpio61 = GPIO_LEVEL_LOW,
+ .gpio62 = GPIO_LEVEL_HIGH,
+ .gpio63 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+ .gpio32 = GPIO_RESET_PWROK,
+ .gpio33 = GPIO_RESET_PWROK,
+ .gpio34 = GPIO_RESET_PWROK,
+ .gpio35 = GPIO_RESET_PWROK,
+ .gpio36 = GPIO_RESET_PWROK,
+ .gpio37 = GPIO_RESET_PWROK,
+ .gpio38 = GPIO_RESET_PWROK,
+ .gpio39 = GPIO_RESET_PWROK,
+ .gpio40 = GPIO_RESET_PWROK,
+ .gpio41 = GPIO_RESET_PWROK,
+ .gpio42 = GPIO_RESET_PWROK,
+ .gpio43 = GPIO_RESET_PWROK,
+ .gpio44 = GPIO_RESET_PWROK,
+ .gpio45 = GPIO_RESET_PWROK,
+ .gpio46 = GPIO_RESET_PWROK,
+ .gpio47 = GPIO_RESET_PWROK,
+ .gpio48 = GPIO_RESET_PWROK,
+ .gpio49 = GPIO_RESET_PWROK,
+ .gpio50 = GPIO_RESET_PWROK,
+ .gpio51 = GPIO_RESET_PWROK,
+ .gpio52 = GPIO_RESET_PWROK,
+ .gpio53 = GPIO_RESET_PWROK,
+ .gpio54 = GPIO_RESET_PWROK,
+ .gpio55 = GPIO_RESET_PWROK,
+ .gpio56 = GPIO_RESET_PWROK,
+ .gpio57 = GPIO_RESET_PWROK,
+ .gpio58 = GPIO_RESET_PWROK,
+ .gpio59 = GPIO_RESET_PWROK,
+ .gpio60 = GPIO_RESET_PWROK,
+ .gpio61 = GPIO_RESET_PWROK,
+ .gpio62 = GPIO_RESET_PWROK,
+ .gpio63 = GPIO_RESET_PWROK,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio73 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+ .gpio75 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_HIGH,
+ .gpio65 = GPIO_LEVEL_HIGH,
+ .gpio66 = GPIO_LEVEL_HIGH,
+ .gpio67 = GPIO_LEVEL_HIGH,
+ .gpio68 = GPIO_LEVEL_HIGH,
+ .gpio69 = GPIO_LEVEL_LOW,
+ .gpio70 = GPIO_LEVEL_LOW,
+ .gpio71 = GPIO_LEVEL_LOW,
+ .gpio72 = GPIO_LEVEL_HIGH,
+ .gpio73 = GPIO_LEVEL_LOW,
+ .gpio74 = GPIO_LEVEL_HIGH,
+ .gpio75 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+ .gpio64 = GPIO_RESET_PWROK,
+ .gpio65 = GPIO_RESET_PWROK,
+ .gpio66 = GPIO_RESET_PWROK,
+ .gpio67 = GPIO_RESET_PWROK,
+ .gpio68 = GPIO_RESET_PWROK,
+ .gpio69 = GPIO_RESET_PWROK,
+ .gpio70 = GPIO_RESET_PWROK,
+ .gpio71 = GPIO_RESET_PWROK,
+ .gpio72 = GPIO_RESET_PWROK,
+ .gpio73 = GPIO_RESET_PWROK,
+ .gpio74 = GPIO_RESET_PWROK,
+ .gpio75 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
new file mode 100644
index 0000000..253ec08
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
@@ -0,0 +1,8 @@
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
new file mode 100644
index 0000000..0124baa
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 Google Inc.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <cbfs.h>
+#include <build.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+const char *smbios_mainboard_bios_version(void)
+{
+ /* Satisfy thinkpad_acpi. */
+ if (strlen(CONFIG_LOCALVERSION))
+ return "CBET4000 " CONFIG_LOCALVERSION;
+ else
+ return "CBET4000 " COREBOOT_VERSION;
+}
+
+
+
+static void mainboard_init(device_t dev)
+{
+ RCBA32(0x38c8) = 0x00002005;
+ RCBA32(0x38c4) = 0x00802005;
+ RCBA32(0x38c0) = 0x00000007;
+ RCBA32(0x2240) = 0x00330e71;
+ RCBA32(0x2244) = 0x003f0eb1;
+ RCBA32(0x2248) = 0x002102cd;
+ RCBA32(0x224c) = 0x00f60000;
+ RCBA32(0x2250) = 0x00020000;
+ RCBA32(0x2254) = 0x00e3004c;
+ RCBA32(0x2258) = 0x00e20bef;
+ RCBA32(0x2260) = 0x003304ed;
+ RCBA32(0x2278) = 0x001107c1;
+ RCBA32(0x227c) = 0x001d07e9;
+ RCBA32(0x2280) = 0x00e20000;
+ RCBA32(0x2284) = 0x00ee0000;
+ RCBA32(0x2288) = 0x005b05d3;
+ RCBA32(0x2318) = 0x04b8ff2e;
+ RCBA32(0x231c) = 0x03930f2e;
+ RCBA32(0x3808) = 0x005044a3;
+ RCBA32(0x3810) = 0x52410000;
+ RCBA32(0x3814) = 0x0000008a;
+ RCBA32(0x3818) = 0x00000006;
+ RCBA32(0x381c) = 0x0000072e;
+ RCBA32(0x3820) = 0x0000000a;
+ RCBA32(0x3824) = 0x00000123;
+ RCBA32(0x3828) = 0x00000009;
+ RCBA32(0x382c) = 0x00000001;
+ RCBA32(0x3834) = 0x0000061a;
+ RCBA32(0x3838) = 0x00000003;
+ RCBA32(0x383c) = 0x00000a76;
+ RCBA32(0x3840) = 0x00000004;
+ RCBA32(0x3844) = 0x0000e5e4;
+ RCBA32(0x3848) = 0x0000000e;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard_smi.c
new file mode 100644
index 0000000..35702f0
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard_smi.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <pc80/mc146818rtc.h>
+#include <delay.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ break;
+ case APM_CNT_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
new file mode 100644
index 0000000..081b682
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -0,0 +1,211 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define SUPERIO_BASE 0x2e
+#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
+#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
+#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <superio/ite/it8728f/it8728f.h>
+#include <superio/ite/common/ite.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+static void it8728f_b75md3v_disable_reboot(device_t dev)
+{
+ /* GPIO SIO settings */
+ ite_reg_write(dev, 0xEF, 0x7E); // magic
+
+ ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
+ ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
+ ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
+ ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
+ ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
+ ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
+ ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
+ ite_reg_write(dev, 0xe9, 0x27); // bus select disable
+ ite_reg_write(dev, 0xf0, 0x10); // ?
+ ite_reg_write(dev, 0xf1, 0x42); // ?
+ ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
+
+ /* EC SIO settings */
+ ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
+ ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
+ ite_reg_write(IT8728F_EC, 0xf9, 0x48);
+ ite_reg_write(IT8728F_EC, 0x60, 0x0a);
+ ite_reg_write(IT8728F_EC, 0x61, 0x30);
+ ite_reg_write(IT8728F_EC, 0x62, 0x0a);
+ ite_reg_write(IT8728F_EC, 0x63, 0x20);
+ ite_reg_write(IT8728F_EC, 0x30, 0x01);
+}
+
+void rcba_config(void)
+{
+/*
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80);
+
+ outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
+
+ RCBA32(0x3500) = 0x2000035f;
+ RCBA32(0x3504) = 0x2000035f;
+ RCBA32(0x3508) = 0x2000035f;
+ RCBA32(0x350c) = 0x2000035f;
+ RCBA32(0x3510) = 0x2000035f;
+ RCBA32(0x3514) = 0x2000035f;
+ RCBA32(0x3518) = 0x2000035f;
+ RCBA32(0x351c) = 0x2000035f;
+ RCBA32(0x3520) = 0x2000035f;
+ RCBA32(0x3524) = 0x2000035f;
+ RCBA32(0x3528) = 0x2000035f;
+ RCBA32(0x352c) = 0x2000035f;
+ RCBA32(0x3530) = 0x2000035f;
+ RCBA32(0x3534) = 0x2000035f;
+ RCBA32(0x3560) = 0x024c8001;
+ RCBA32(0x3564) = 0x000024a3;
+ RCBA32(0x3568) = 0x00040002;
+ RCBA32(0x356c) = 0x01000050;
+ RCBA32(0x3570) = 0x02000662;
+ RCBA32(0x3574) = 0x18000f9f;
+ RCBA32(0x3578) = 0x1800ff4f;
+ RCBA32(0x357c) = 0x0001d530;
+ RCBA32(0x35a0) = 0xc0300c03;
+ RCBA32(0x35a4) = 0x00241803;
+
+ pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
+
+ outw (0x0000, DEFAULT_PMBASE | 0x003c);
+
+ RCBA32(0x2240) = 0x00330e71;
+ RCBA32(0x2244) = 0x003f0eb1;
+ RCBA32(0x2248) = 0x002102cd;
+ RCBA32(0x224c) = 0x00f60000;
+ RCBA32(0x2250) = 0x00020000;
+ RCBA32(0x2254) = 0x00e3004c;
+ RCBA32(0x2258) = 0x00e20bef;
+ RCBA32(0x2260) = 0x003304ed;
+ RCBA32(0x2278) = 0x001107c1;
+ RCBA32(0x227c) = 0x001d07e9;
+ RCBA32(0x2280) = 0x00e20000;
+ RCBA32(0x2284) = 0x00ee0000;
+ RCBA32(0x2288) = 0x005b05d3;
+ RCBA32(0x2318) = 0x04b8ff2e;
+ RCBA32(0x231c) = 0x03930f2e;
+// RCBA32(0x3418) = 0x1fee1fe1;
+ RCBA32(0x3808) = 0x005044a3;
+ RCBA32(0x3810) = 0x52410000;
+ RCBA32(0x3814) = 0x0000008a;
+ RCBA32(0x3818) = 0x00000006;
+ RCBA32(0x381c) = 0x0000072e;
+ RCBA32(0x3820) = 0x0000000a;
+ RCBA32(0x3824) = 0x00000123;
+ RCBA32(0x3828) = 0x00000009;
+ RCBA32(0x382c) = 0x00000001;
+ RCBA32(0x3834) = 0x0000061a;
+ RCBA32(0x3838) = 0x00000003;
+ RCBA32(0x383c) = 0x00000a76;
+ RCBA32(0x3840) = 0x00000004;
+ RCBA32(0x3844) = 0x0000e5e4;
+ RCBA32(0x3848) = 0x0000000e;
+*/
+ /* Disable unused devices (board specific) */
+ RCBA32(FD) = 0x17ee1fe1;
+
+ /* Enable HECI */
+ RCBA32(FD2) &= ~0x2;
+}
+
+void pch_enable_lpc(void)
+{
+ /*
+ * Enable:
+ * EC Decode Range PortA30/A20
+ * SuperIO Port2E/2F
+ * PS/2 Keyboard/Mouse Port60/64
+ * FDD Port3F0h-3F5h and Port3F7h
+ */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+
+ pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+
+ /* Initialize SuperIO */
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8728f_b75md3v_disable_reboot(SUPERIO_GPIO);
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 5, 0 },
+ { 1, 5, 0 },
+ { 1, 5, 1 },
+ { 1, 5, 1 },
+ { 1, 5, 2 },
+ { 1, 5, 2 },
+ { 1, 5, 3 },
+ { 1, 5, 3 },
+ { 1, 5, 4 },
+ { 1, 5, 4 },
+ { 1, 5, 6 },
+ { 1, 5, 5 },
+ { 1, 5, 5 },
+ { 1, 5, 6 },
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
+ read_spd (&spd[0], 0x50);
+ read_spd (&spd[1], 0x51);
+ read_spd (&spd[2], 0x52);
+ read_spd (&spd[3], 0x53);
+}
+
+#if 0
+static void dmi_config(void)
+{
+ DMIBAR32(0x0218) = 0x06aa0b0c;
+ DMIBAR32(0x021c) = 0x0b0d0b0d;
+ DMIBAR32(0x0300) = 0x0011028d;
+ DMIBAR32(0x0304) = 0x002102cd;
+ DMIBAR32(0x030c) = 0x007d004b;
+ DMIBAR32(0x0310) = 0x007e004c;
+ DMIBAR32(0x0318) = 0x002304ad;
+ DMIBAR32(0x031c) = 0x003304ed;
+ DMIBAR32(0x03b8) = 0x005c05a4;
+ DMIBAR32(0x03bc) = 0x006c05e4;
+ DMIBAR32(0x0530) = 0x41d3b000;
+ DMIBAR32(0x0534) = 0x00019f80;
+ DMIBAR32(0x0ba4) = 0x0000000d;
+ DMIBAR32(0x0d80) = 0x1c9cfc0b;
+ DMIBAR32(0x0e1c) = 0x20000000;
+ DMIBAR32(0x0e2c) = 0x20000000;
+}
+#endif
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h
new file mode 100644
index 0000000..ed08c8a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef GAB75MD3H_THERMAL_H
+#define GAB75MD3H_THERMAL_H
+
+ /* Temperature which OS will shutdown at */
+ #define CRITICAL_TEMPERATURE 100
+
+ /* Temperature which OS will throttle CPU */
+ #define PASSIVE_TEMPERATURE 90
+
+#endif
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index c323f73..d8f98c1 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -868,7 +868,7 @@ static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a,
0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e,
0x1c4f, 0x1c50, 0x1c52, 0x1c54,
0x1e55, 0x1c56, 0x1e57, 0x1c5c,
- 0x1e5d, 0x1e5e, 0x1e5f,
+ 0x1e5d, 0x1e5e, 0x1e5f, 0x1e49,
0 };
static const struct pci_driver pch_lpc __pci_driver = {
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