[coreboot-gerrit] New patch to review for coreboot: 96a10e9 Fix "enable upper 128bytes of CMOS" It should be this way RCBA32(RC) |= (1 << 2); and no need to "enable" it again in raminit.c

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9801

-gerrit

commit 96a10e9c81fc63f56aeef15abf070b1558ebe30b
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sun Apr 19 10:58:41 2015 +0200

    Fix "enable upper 128bytes of CMOS"
    It should be this way RCBA32(RC) |= (1 << 2);
    and no need to "enable" it again in raminit.c
    
    Change-Id: I12d8689b5b5238f46fa834b9d30bf689eb0c8114
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/northbridge/intel/i945/early_init.c | 2 +-
 src/northbridge/intel/i945/raminit.c    | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 776c051..ea92ce1 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -172,7 +172,7 @@ static void i945_setup_bars(void)
 	printk(BIOS_DEBUG, " done.\n");
 
 	/* Enable upper 128bytes of CMOS */
-	RCBA32(0x3400) = (1 << 2);
+	RCBA32(RC) |= (1 << 2);
 
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	/* Set up all hardcoded northbridge BARs */
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index c3f9bae..bd6e0c9 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2738,8 +2738,6 @@ static void sdram_program_receive_enable(struct sys_info *sysinfo)
 {
 	MCHBAR32(REPC) |= (1 << 0);
 
-	/* enable upper CMOS */
-	RCBA32(0x3400) = (1 << 2);
 
 	/* Program Receive Enable Timings */
 	if (sysinfo->boot_path == BOOT_PATH_RESUME) {