[coreboot-gerrit] Patch merged into coreboot/master: a32b6b9 soc/intel/common: Add function to protect MRC cache

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a32b6b9471696951b99d577882508eb9e526eadc
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Jan 15 15:49:07 2015 -0800

    soc/intel/common: Add function to protect MRC cache
    
    Add support for applying write protection to the MRC cache
    region in SPI flash.
    
    This is only enabled if there is write protect GPIO that is
    set, and the flash status register reports that the flash
    chip is currently write protected.
    
    Then it will call out to a SOC specific function that will
    enable write protection on the RW_MRC_CACHE region of flash.
    
    The implementation is not quite as clean as I would like because
    there is not a common flash protect interface across SOCs so
    instead it relies on a new Kconfig variable to be set that will
    indicate a SOC implements the function to protect a region of
    SPI flash.
    
    BUG=chrome-os-partner:28234
    BRANCH=broadwell
    TEST=build and boot on samus
    1) with either WPSW=0 or SRP0=0 the PRR is not applied
    2) with both WPSW=1 and SRP0=1 the PRR is applied
    
    Change-Id: If5907b7ddf3f966c546ae32dc99aa815beb27587
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: a3e0e71dfd7339aab171a26b67aec465a3f332d6
    Original-Change-Id: I94e54e4723b1dcdacbb6a05f047d0c0ebc7d8711
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/241170
    Original-Reviewed-by: Shawn N <shawnn at chromium.org>
    Reviewed-on: http://review.coreboot.org/9494
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9494 for details.

-gerrit