[coreboot-gerrit] New patch to review for coreboot: 35f2f08 broadwell: Disable XHCI compliance mode entry

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9782

-gerrit

commit 35f2f0863dfa6b703cfab3de8afeedc986cc14b8
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Feb 19 16:21:10 2015 -0800

    broadwell: Disable XHCI compliance mode entry
    
    To avoid entries with Type-C alternate mode devices disable
    compliance mode entry.  This needs to be set on both boot
    and resume.
    
    BUG=chrome-os-partner:35320
    BRANCH=samus
    TEST=manual:
    1) boot on samus with USB keyboard plugged in -> controller in D0 at boot
    2) iotools mmio_read32 0xe12080ec == 0x18010c01
    3) suspend and resume
    4) iotools mmio_read32 0xe12080ec == 0x18010c01
    5) remove USB keyboard -> controller in D3
    6) iotools mmio_read32 0xe12080ec == 0xffffffff
    7) plug in USB keyboard -> controller in D0
    8) iotools mmio_read32 0xe12080ec == 0x18010c01
    9) boot with no external USB devices -> controller in D3 at boot
    10) iotools mmio_read32 0xe12080ec == 0xffffffff
    11) plug in USB keyboard -> controller in D0
    12) iotools mmio_read32 0xe12080ec == 0x18010c01
    
    Change-Id: I4d566112b3c188bafdf9a4bbd92944c89500e3e8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: db8c8ab8ff25f6a39cd50dcc91b5ba9fd7d05059
    Original-Change-Id: I8b68ba75e254a7e236c869f4470207eb5290053d
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/251361
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/soc/intel/broadwell/xhci.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 4c721c2..83d50b8 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -192,11 +192,30 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
 }
 #else /* !__SMM__ */
 
+static void xhci_init(struct device *dev)
+{
+	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	u16 reg16;
+	u32 reg32;
+
+	/* Ensure controller is in D0 state */
+	reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
+	reg16 &= ~XHCI_PWR_CTL_SET_MASK;
+	reg16 |= XHCI_PWR_CTL_SET_D0;
+	pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
+
+	/* Disable Compliance Mode Entry */
+	reg32 = read32(res->base + 0x80ec);
+	reg32 |= (1 << 0);
+	write32(res->base + 0x80ec, reg32);
+}
+
 static struct device_operations usb_xhci_ops = {
 	.read_resources		= &pci_dev_read_resources,
 	.set_resources		= &pci_dev_set_resources,
 	.enable_resources	= &pci_dev_enable_resources,
 	.ops_pci		= &broadwell_pci_ops,
+	.init			= &xhci_init,
 };
 
 static const unsigned short pci_device_ids[] = {