[coreboot-gerrit] New patch to review for coreboot: ca28c65 chromeos: Provide common watchdog reboot support
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Apr 16 14:23:14 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9749
-gerrit
commit ca28c65f1fdcfc4ef083d2f211b0c26e1c88cbc7
Author: Julius Werner <jwerner at chromium.org>
Date: Wed Jan 21 17:39:49 2015 -0800
chromeos: Provide common watchdog reboot support
Many ChromeOS devices use a GPIO to reset the system, in order to
guarantee that the TPM cannot be reset without also resetting the CPU.
Often chipset/SoC hardware watchdogs trigger some kind of built-in
CPU reset, bypassing this GPIO and thus leaving the TPM locked. These
ChromeOS devices need to detect that condition in their bootblock and
trigger a second (proper) reboot.
This patch adds some code to generalize this previously
mainboard-specific functionality and uses it on Veyron boards. It also
provides some code to add the proper eventlog entry for a watchdog
reset. Since the second reboot has to happen before firmware
verification and the eventlog is usually only initialized afterwards, we
provide the functionality to place a tombstone in a memlayout-defined
location (which could be SRAM or some MMIO register that is preserved
across reboots).
[pg: Integrates
'mips: Temporarily work around build error caused by <arch/io.h> mismatch]
BRANCH=veyron
BUG=chrome-os-partner:35705
TEST=Run 'mem w 0xff800000 0x9' on a Jerry, watch how a "Hardware
watchdog reset" event appears in the eventlog after the reboot.
Change-Id: I0a33820b236c9328b2f9b20905b69cb934326f2a
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: fffc484bb89f5129d62739dcb44d08d7f5b30b33
Original-Change-Id: I7ee1d02676e9159794d29e033d71c09fdf4620fd
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242404
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Commit-Id: c919c72ddc9d2e1e18858c0bf49c0ce79f2bc506
Original-Change-Id: I509c842d3393bd810e89ebdf0dc745275c120c1d
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242504
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
src/mainboard/google/veyron_jerry/bootblock.c | 6 ++--
src/mainboard/google/veyron_jerry/mainboard.c | 1 +
src/mainboard/google/veyron_mighty/bootblock.c | 6 ++--
src/mainboard/google/veyron_mighty/mainboard.c | 1 +
src/mainboard/google/veyron_pinky/bootblock.c | 6 ++--
src/mainboard/google/veyron_pinky/mainboard.c | 1 +
src/mainboard/google/veyron_speedy/bootblock.c | 6 ++--
src/mainboard/google/veyron_speedy/mainboard.c | 1 +
src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 +
src/vendorcode/google/chromeos/Makefile.inc | 4 +++
src/vendorcode/google/chromeos/chromeos.h | 6 ++++
src/vendorcode/google/chromeos/memlayout.h | 4 +++
src/vendorcode/google/chromeos/symbols.h | 4 +++
src/vendorcode/google/chromeos/watchdog.c | 42 ++++++++++++++++++++++++
14 files changed, 73 insertions(+), 16 deletions(-)
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 90ad744..acf81bc 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -58,10 +58,8 @@ void bootblock_mainboard_init(void)
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
- if (rkclk_was_watchdog_reset()) {
- printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
- hard_reset();
- }
+ if (rkclk_was_watchdog_reset())
+ reboot_from_watchdog();
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c
index 00060a7..1fc823c 100644
--- a/src/mainboard/google/veyron_jerry/mainboard.c
+++ b/src/mainboard/google/veyron_jerry/mainboard.c
@@ -123,6 +123,7 @@ static void mainboard_init(device_t dev)
configure_vop();
elog_init();
+ elog_add_watchdog_reset();
elog_add_boot_reason();
}
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 90ad744..acf81bc 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -58,10 +58,8 @@ void bootblock_mainboard_init(void)
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
- if (rkclk_was_watchdog_reset()) {
- printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
- hard_reset();
- }
+ if (rkclk_was_watchdog_reset())
+ reboot_from_watchdog();
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
diff --git a/src/mainboard/google/veyron_mighty/mainboard.c b/src/mainboard/google/veyron_mighty/mainboard.c
index 540b23d..fb1d8fa 100644
--- a/src/mainboard/google/veyron_mighty/mainboard.c
+++ b/src/mainboard/google/veyron_mighty/mainboard.c
@@ -123,6 +123,7 @@ static void mainboard_init(device_t dev)
configure_vop();
elog_init();
+ elog_add_watchdog_reset();
elog_add_boot_reason();
}
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 90ad744..acf81bc 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -58,10 +58,8 @@ void bootblock_mainboard_init(void)
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
- if (rkclk_was_watchdog_reset()) {
- printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
- hard_reset();
- }
+ if (rkclk_was_watchdog_reset())
+ reboot_from_watchdog();
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
index c6636b1..e3e5b29 100644
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -167,6 +167,7 @@ static void mainboard_init(device_t dev)
configure_vop();
elog_init();
+ elog_add_watchdog_reset();
elog_add_boot_reason();
}
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 90ad744..acf81bc 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -58,10 +58,8 @@ void bootblock_mainboard_init(void)
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
- if (rkclk_was_watchdog_reset()) {
- printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
- hard_reset();
- }
+ if (rkclk_was_watchdog_reset())
+ reboot_from_watchdog();
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
diff --git a/src/mainboard/google/veyron_speedy/mainboard.c b/src/mainboard/google/veyron_speedy/mainboard.c
index 540b23d..fb1d8fa 100644
--- a/src/mainboard/google/veyron_speedy/mainboard.c
+++ b/src/mainboard/google/veyron_speedy/mainboard.c
@@ -123,6 +123,7 @@ static void mainboard_init(device_t dev)
configure_vop();
elog_init();
+ elog_add_watchdog_reset();
elog_add_boot_reason();
}
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 8a12aba..632384c 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -47,5 +47,6 @@ SECTIONS
/* 4K of special SRAM in PMU power domain.
* Careful: only supports 32-bit wide write accesses! */
SYMBOL(pmu_sram, 0xFF720000)
+ WATCHDOG_TOMBSTONE(0xFF720FFC, 4)
SYMBOL(epmu_sram, 0xFF721000)
}
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 8d0360c..1a976af 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -42,6 +42,10 @@ ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
smm-y += fmap.c
romstage-y += vpd_decode.c cros_vpd.c
ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_calibration.c
+ifeq ($(CONFIG_ARCH_X86)$(CONFIG_ARCH_MIPS),)
+bootblock-y += watchdog.c
+ramstage-y += watchdog.c
+endif
ifeq ($(MOCK_TPM),1)
CFLAGS_common += -DMOCK_TPM=1
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index 1184fa5..ccbadab 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -39,9 +39,15 @@ void init_chromeos(int bootmode);
/* functions implemented in elog.c */
void elog_add_boot_reason(void);
+
+/* functions implemented in watchdog.c */
+void elog_add_watchdog_reset(void);
+void reboot_from_watchdog(void);
#else
static inline void init_chromeos(int bootmode) { }
static inline void elog_add_boot_reason(void) { return; }
+static inline void elog_add_watchdog_reset(void) { return; }
+static inline void reboot_from_watchdog(void) { return; }
#endif /* CONFIG_CHROMEOS */
struct romstage_handoff;
diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h
index 140da46..a7ea32e 100644
--- a/src/vendorcode/google/chromeos/memlayout.h
+++ b/src/vendorcode/google/chromeos/memlayout.h
@@ -47,4 +47,8 @@
#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
#endif
+#define WATCHDOG_TOMBSTONE(addr, size) \
+ REGION(watchdog_tombstone, addr, size, 4) \
+ _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
+
#endif /* __CHROMEOS_MEMLAYOUT_H */
diff --git a/src/vendorcode/google/chromeos/symbols.h b/src/vendorcode/google/chromeos/symbols.h
index 21169f0..77b51b8 100644
--- a/src/vendorcode/google/chromeos/symbols.h
+++ b/src/vendorcode/google/chromeos/symbols.h
@@ -29,4 +29,8 @@ extern u8 _verstage[];
extern u8 _everstage[];
#define _verstage_size (_everstage - _verstage)
+extern u8 _watchdog_tombstone[];
+extern u8 _ewatchdog_tombstone[];
+#define _watchdog_tombstone_size (_ewatchdog_tombstone - _watchdog_tombstone)
+
#endif /* __CHROMEOS_SYMBOLS_H */
diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c
new file mode 100644
index 0000000..e4adf8a
--- /dev/null
+++ b/src/vendorcode/google/chromeos/watchdog.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <elog.h>
+#include <reset.h>
+
+#include "chromeos.h"
+#include "symbols.h"
+
+#define WATCHDOG_TOMBSTONE_MAGIC 0x9d2f41a7
+
+void elog_add_watchdog_reset(void)
+{
+ if (readl(_watchdog_tombstone) == WATCHDOG_TOMBSTONE_MAGIC)
+ elog_add_event(ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED);
+ writel(0, _watchdog_tombstone);
+}
+
+void reboot_from_watchdog(void)
+{
+ printk(BIOS_INFO, "Last reset was watchdog, reboot again to reset TPM!\n");
+ writel(WATCHDOG_TOMBSTONE_MAGIC, _watchdog_tombstone);
+ hard_reset();
+}
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