[coreboot-gerrit] Patch set updated for coreboot: acf6cff pistachio: report UART register width

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9740

-gerrit

commit acf6cffa92c4b8bdb5f924a3548a6bb0c8e0e986
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Jan 9 16:55:36 2015 -0800

    pistachio: report UART register width
    
    Pistachio UART closely matches 8250, the only difference is that its
    register file is mapped to a 32 bit bus.
    
    Provide a function to report register with so that the Coreboot table
    entry gets correct value.
    
    BRANCH=none
    BUG=chrome-os-partner:31438
    TEST=with the rest of the patches integrated depthcharge console messages
         show up when running on the FPGA board
    
    Change-Id: Icd72b115b4f339800d6c8b210a6617398232f806
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e1dc4156949b20efafbca2c19ff424436a400087
    Original-Change-Id: Icafb014af338e05bbf1044b791683733685ffab3
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/240028
    Original-Reviewed-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/imgtec/pistachio/uart.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c
index ff91459..ee5da57 100644
--- a/src/soc/imgtec/pistachio/uart.c
+++ b/src/soc/imgtec/pistachio/uart.c
@@ -179,7 +179,7 @@ void uart_fill_lb(void *data)
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 	serial.baud = default_baudrate();
-	serial.regwidth = 1;
+	serial.regwidth = 1 << UART_SHIFT;
 	lb_add_serial(&serial, data);
 
 	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);