[coreboot-gerrit] Patch set updated for coreboot: e30c28d storm: use different CBFS caches before and after DRAM is available

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9688

-gerrit

commit e30c28dbecab5953724eeff4dd950244a6d9855b
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Thu Dec 11 17:31:20 2014 -0800

    storm: use different CBFS caches before and after DRAM is available
    
    Booting depthcharge requires much larger CBFS cache, but by the time
    depthcharge is being booted DRAM is already initialized. Use different
    memory spaces for CBFS cache before and after DRAM is available.
    
    Also, make sure that CBMEM uses memory below CBFS cache in DRAM.
    
    BRANCH=storm
    BUG=chrome-os-partner:34161
    TEST=with this change on Storm ramstage finds and boots depthcharge in
         recovery mode
    
    Change-Id: Icd1bbf4bcc5f9d92b2653b5a8891409105a25353
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e1e0b029b7fb09b84784373150cc4ce9eea7b3f5
    Original-Change-Id: I33fd97806b2db6fab2adc44b67e5f54258642967
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/234543
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/qualcomm/ipq806x/cbmem.c                    |  5 ++---
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld   | 13 +++++++++++++
 src/soc/qualcomm/ipq806x/include/soc/soc_services.h |  4 ++++
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c
index fdf2605..782f752 100644
--- a/src/soc/qualcomm/ipq806x/cbmem.c
+++ b/src/soc/qualcomm/ipq806x/cbmem.c
@@ -18,10 +18,9 @@
  */
 
 #include <cbmem.h>
-#include <stddef.h>
-#include <symbols.h>
+#include <soc/soc_services.h>
 
 void *cbmem_top(void)
 {
-	return (void *)((uintptr_t)_dram + CONFIG_DRAM_SIZE_MB*MiB);
+	return _memlayout_cbmem_top;
 }
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index 7020f92..873f61c 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -39,11 +39,24 @@ SECTIONS
 	QCA_SHARED_RAM(2A03F000, 4K)
 */
 	STACK(0x2A040000, 16K)
+#ifdef __PRE_RAM__
+       /*
+        * ipq8064 is different from most other ARM platforms: it loads the
+	* proprietary DRAM initialization code from CBFS (as opposed to compiling
+	* it in into rombase). As a result CBFS needs to be used before DRAM is
+	* availale, which means CBFS cache must be in SRAM, which in turn means
+	* that PRERAM_CBFS_CACHE description can not be used here.
+	*/
 	CBFS_CACHE(0x2A044000, 96K)
+#endif
 	TTB(0x2A05C000, 16K)
 	SRAM_END(0x2A060000)
 
 	DRAM_START(0x40000000)
 	RAMSTAGE(0x40640000, 128K)
+	SYMBOL(memlayout_cbmem_top, 0x59FA0000)
+#ifndef __PRE_RAM__
+	CBFS_CACHE(0x59FA0000, 256K)
+#endif
 	DMA_COHERENT(0x5A000000, 2M)
 }
diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
index 8a936fe..9e92bc7 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
+++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
@@ -20,6 +20,10 @@
 #ifndef __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__
 #define __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__
 
+#include <types.h>
+
+extern u8 _memlayout_cbmem_top[];
+
 /* Returns zero on success, nonzero on failure. */
 int initialize_dram(void);