[coreboot-gerrit] Patch set updated for coreboot: 206a994 rk3288: Fix failing LPDDR3 reboot test

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9654

-gerrit

commit 206a994fdcb80743745413f926edf5141114a3af
Author: jinkun.hong <jinkun.hong at rock-chips.com>
Date:   Wed Jan 21 15:47:25 2015 +0800

    rk3288: Fix failing LPDDR3 reboot test
    
    tMRD request 10nCK in LPDDR3, we set the DDR_PCTL_TMRD BIT0~BIT2 to generate
    this signal, but the max value we can set is 7, can not meet the standard.So,
    now we send the Mode Register Set command manual,and we can add the delay
    manual.
    
    BUG=chrome-os-partner:34608
    TEST=loop reboot
    BRANCH=veyron
    
    Change-Id: Id974ab935c2df6ea35dcdd240378ffc68de0204d
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: b60a4de6ff3ad3720c2c06ed7de03ed942360e6c
    Original-Change-Id: I0d29ea9cd82ef018e835ae53090a47d0299ef61d
    Original-Signed-off-by: jinkun.hong <jinkun.hong at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/242176
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/soc/rockchip/rk3288/sdram.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c
index d330f99..cda36be 100644
--- a/src/soc/rockchip/rk3288/sdram.c
+++ b/src/soc/rockchip/rk3288/sdram.c
@@ -998,12 +998,29 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
 		writel(POWER_UP_START, &ddr_pctl_regs->powctl);
 		while (!(readl(&ddr_pctl_regs->powstat) & POWER_UP_DONE))
 			;
-		send_command(ddr_pctl_regs, 3, DESELECT_CMD, 0);
-		udelay(1);
-		send_command(ddr_pctl_regs, 3, PREA_CMD, 0);
 
 		memory_init(ddr_publ_regs, sdram_params->dramtype);
 		move_to_config_state(ddr_publ_regs, ddr_pctl_regs);
+
+		if (sdram_params->dramtype == LPDDR3) {
+			send_command(ddr_pctl_regs, 3, DESELECT_CMD, 0);
+			udelay(1);
+			send_command(ddr_pctl_regs, 3, PREA_CMD, 0);
+			udelay(1);
+			send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(63) |
+				LPDDR2_OP(0xFC));
+			udelay(1);
+			send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(1) |
+				LPDDR2_OP(sdram_params->phy_timing.mr[1]));
+			udelay(1);
+			send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(2) |
+				LPDDR2_OP(sdram_params->phy_timing.mr[2]));
+			udelay(1);
+			send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(3) |
+				LPDDR2_OP(sdram_params->phy_timing.mr[3]));
+			udelay(1);
+		}
+
 		set_bandwidth_ratio(channel, sdram_params->ch[channel].bw);
 		/*
 		 * set cs