[coreboot-gerrit] Patch set updated for coreboot: 1cb7de9 veyron_speedy: Support samsung-4GB and hynix-4GB lpddr

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9628

-gerrit

commit 1cb7de9a8cddf95e2bc2bbe5816f0a3ddad19dca
Author: huang lin <hl at rock-chips.com>
Date:   Tue Dec 9 09:49:21 2014 +0800

    veyron_speedy: Support samsung-4GB and hynix-4GB lpddr
    
    Add the samsung-4GB and hynix-4GB lpddr inf file,
    use ram_id 1000 correspond to samsung-4GB lpddr,
    and use ram_id 1001 correspond to hynix-4GB lpddr.
    
    BUG=chrome-os-partner:33269
    TEST=Boot veyron_speedy normal
    BRANCH=None
    
    Change-Id: I21983c48e1e99aa70ae9bb3fb6550ae9af472015
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: d34b19dc9b57b4f31dc1b28581f3f8fc0fcc7e6b
    Original-Change-Id: I55b6968c642df8c1f579e518232ab5d278e7e12f
    Original-Signed-off-by: huang lin <hl at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/233859
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/mainboard/google/veyron_speedy/sdram_configs.c |  4 +-
 .../sdram_inf/sdram-lpddr3-hynix-4GB.inc           | 77 ++++++++++++++++++++++
 .../sdram_inf/sdram-lpddr3-samsung-4GB.inc         | 77 ++++++++++++++++++++++
 3 files changed, 156 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c
index 3593758..06b67dd 100644
--- a/src/mainboard/google/veyron_speedy/sdram_configs.c
+++ b/src/mainboard/google/veyron_speedy/sdram_configs.c
@@ -33,8 +33,8 @@ static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 0101 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 0110 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 0111 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1000 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1001 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc"	/* ram_code = 1000 */
+#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 1010 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 1011 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
new file mode 100644
index 0000000..ef943e1
--- /dev/null
+++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
@@ -0,0 +1,77 @@
+{
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 1
+},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
new file mode 100644
index 0000000..d56897a
--- /dev/null
+++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
@@ -0,0 +1,77 @@
+{
+	{
+		{
+			.rank = 0x2,
+			.col = 0xB,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		},
+		{
+			.rank = 0x2,
+			.col = 0xB,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 6,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 1
+},