[coreboot-gerrit] New patch to review for coreboot: 69a20d0 ipq806x: modify imem layout

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9683

-gerrit

commit 69a20d09572e0db8b07a7c16140f44767ba530e4
Author: Deepa Dinamani <deepad at codeaurora.org>
Date:   Mon Oct 27 15:40:05 2014 -0700

    ipq806x: modify imem layout
    
    With introduction of uber-sbl SRAM usage pattern is changing, this
    introduces the new memory layout.
    
    This patch overlays DDR initialization code with uber-sbl, as uber-sbl
    goes out of scope as soon as bootblock starts.
    
    A 4K block at offset 0x3f000 added in the comments, this is a shared
    structure used by different QCA modules.
    
    This suggested layout is not final, but will allow to move closer to
    the production image.
    
    BRANCH=storm
    BUG=chrome-os-partner:34161
    TEST=with other patches applied Storm boots all the way to rombase and
         initializes DRAM.
    
    Change-Id: I46af81b39b09935aa7fffdabda223e7e64c7a446
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a20c0570361038c0ae406dcb1f4bc657eea120f6
    Original-Change-Id: I927f6ffc524fc8f0effd7b91d3f5d1e8d6be1530
    Original-Signed-off-by: Deepa Dinamani <deepad at codeaurora.org>
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/229023
---
 src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 29 +++++++++++++++--------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index de1b129..7020f92 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -18,23 +18,32 @@
  */
 
 #include <memlayout.h>
+#include <vendorcode/google/chromeos/vboot2/memlayout.h>
 
 #include <arch/header.ld>
 
-/* TODO: This should be revised by someone who understands the SoC better. */
-
 SECTIONS
 {
-	/* TODO: add SRAM_START(), SRAM_END() and REGION(reserved_sbl) */
-	TTB(0x2A05C000, 48K)
+	SRAM_START(0x2A000000)
+	/* This includes bootblock image, can be reused after bootblock starts */
+/*	UBER_SBL(0x2A000000, 48K) */
+/*	DDR(0x2A000000, 48K) */
+	BOOTBLOCK(0x2A00C000, 24K)
+	OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K)
+	VBOOT2_WORK(0x2A022000, 16K)
+	PRERAM_CBMEM_CONSOLE(0x2A026000, 32K)
+/*	0x2e000..0x3F000  68 KB free */
+
+/* Keep the below area reserved at all times, it is used by various QCA
+   components as shared data
+	QCA_SHARED_RAM(2A03F000, 4K)
+*/
+	STACK(0x2A040000, 16K)
+	CBFS_CACHE(0x2A044000, 96K)
+	TTB(0x2A05C000, 16K)
+	SRAM_END(0x2A060000)
 
 	DRAM_START(0x40000000)
-	CBFS_CACHE(0x405C0000, 240K)
-	STACK(0x405FC000, 16K)
-	/* TODO: "256K bytes left for TZBSP"... what does that mean? */
-	BOOTBLOCK(0x40600000, 32K)
-	PRERAM_CBMEM_CONSOLE(0x40618000, 8K)
-	ROMSTAGE(0x40620000, 128K)
 	RAMSTAGE(0x40640000, 128K)
 	DMA_COHERENT(0x5A000000, 2M)
 }