[coreboot-gerrit] Patch merged into coreboot/master: 0f58d0b urara: Reduce MIPS PLL jitter

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 0f58d0b941559c627153943891737cf8fb0a7430
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Tue Feb 3 00:26:08 2015 +0000

    urara: Reduce MIPS PLL jitter
    
    The current MIPS PLL is configured in such a way that there is
    excessive jitter.  Correct this by applying new PLL settings. The
    resultant frequency is 546MHz instead of 550MHz.
    
    BUG=chrome-os-partner:31438
    TEST=tested on Pistachio bring up board as part of the JTAG
         loading script;
    BRANCH=none
    
    Change-Id: Ica1bfff29e01819b86cd2bb8b18d8adc9dfa3260
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 0c04354b49b73d234492521d81b6600d487175b0
    Original-Change-Id: I28b41b1e82dbdf9da21bf0ab74f9722cdad923f1
    Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/245620
    Original-Reviewed-by: James Hartley <james.hartley at imgtec.com>
    Original-Reviewed-by: Andrew Bresticker <abrestic at chromium.org>
    Reviewed-on: http://review.coreboot.org/9671
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9671 for details.

-gerrit