[coreboot-gerrit] Patch set updated for coreboot: d4211a2 veyron: add H9CCNNN8GTMLAR sdram in speedy

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9640

-gerrit

commit d4211a247c490ae235467d693242c635b831c40b
Author: Jiazi Yang <Tomato_Yang at asus.com>
Date:   Wed Dec 24 04:11:14 2014 -0500

    veyron: add H9CCNNN8GTMLAR sdram in speedy
    
    BRANCH=None
    TEST=emerge-veyron_speedy coreboot
    BUG=None
    
    Change-Id: Iab377e93472db0b7778df020afa84ee97f0e4079
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: fedf6ed7dc220d58ad10d49ac9ea02443746e77e
    Original-Change-Id: Id5024bfd32a0aa1fb00f3af8dc337ccccaf40729
    Original-Signed-off-by: Jiazi Yang <Tomato_Yang at asus.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/237544
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Trybot-Ready: Julius Werner <jwerner at chromium.org>
---
 src/mainboard/google/veyron_speedy/sdram_configs.c |  2 +-
 .../sdram_inf/sdram-lpddr3-hynix-2GB.inc           | 78 ++++++++++++++++++++++
 2 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c
index 06b67dd..2313e68 100644
--- a/src/mainboard/google/veyron_speedy/sdram_configs.c
+++ b/src/mainboard/google/veyron_speedy/sdram_configs.c
@@ -26,7 +26,7 @@
 
 static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0001 */
+#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
 #include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
new file mode 100644
index 0000000..ff56c72
--- /dev/null
+++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Hynix H9CCNNN8GTMLAR chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 14,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 1
+},