[coreboot-gerrit] Patch set updated for coreboot: 236f41e libpayload: Add dwc2 usb driver
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Apr 14 09:20:33 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9453
-gerrit
commit 236f41e55c1c541a8069572d979182d3441a2a2b
Author: huang lin <hl at rock-chips.com>
Date: Wed Aug 6 16:43:43 2014 +0800
libpayload: Add dwc2 usb driver
BUG=chrome-os-partner:29778
TEST=emerge-veyron libpayload
Change-Id: I33f312a939e600b8f4e50a092bb61c5d6bc6d741
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 39ffe53336a2a3b2baa067cdd3dccca5ae93f68e
Original-Change-Id: Idad1ad165fd44df635a0cb13bfec6fada1378bc8
Original-Signed-off-by: huang lin <hl at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211053
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
payloads/libpayload/Config.in | 6 +
payloads/libpayload/configs/config.arm64-generic | 1 +
payloads/libpayload/configs/defconfig | 1 +
payloads/libpayload/configs/defconfig-arm | 1 +
payloads/libpayload/drivers/Makefile.inc | 2 +
payloads/libpayload/drivers/usb/dwc2.c | 356 +++++++++++++
payloads/libpayload/drivers/usb/dwc2.h | 27 +
payloads/libpayload/drivers/usb/dwc2_private.h | 643 +++++++++++++++++++++++
payloads/libpayload/drivers/usb/dwc2_rh.c | 188 +++++++
payloads/libpayload/drivers/usb/usbinit.c | 5 +
payloads/libpayload/include/usb/usb.h | 2 +-
11 files changed, 1231 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in
index 2efd5d6..b1b903b 100644
--- a/payloads/libpayload/Config.in
+++ b/payloads/libpayload/Config.in
@@ -470,6 +470,12 @@ config USB_XHCI
Select this option if you want to use USB 3.0
NOTE: This option is not (fully) implemented yet
+config USB_DWC2
+ bool "Support for USB DesignWare HCD controllers"
+ depends on USB && !USB_HID
+ help
+ Select this option if you want to use DesignWare USB 2.0 host controller
+
config USB_HID
bool "Support for USB keyboards"
depends on USB
diff --git a/payloads/libpayload/configs/config.arm64-generic b/payloads/libpayload/configs/config.arm64-generic
index d44237e..986ebe1 100644
--- a/payloads/libpayload/configs/config.arm64-generic
+++ b/payloads/libpayload/configs/config.arm64-generic
@@ -60,6 +60,7 @@ CONFIG_LP_USB_HID=y
CONFIG_LP_USB_HUB=y
CONFIG_LP_USB_MSC=y
CONFIG_LP_USB_GEN_HUB=y
+# CONFIG_LP_USB_DWC2 is not set
# CONFIG_LP_USB_PCI is not set
# CONFIG_LP_BIG_ENDIAN is not set
CONFIG_LP_LITTLE_ENDIAN=y
diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig
index 556b619..a518da5 100644
--- a/payloads/libpayload/configs/defconfig
+++ b/payloads/libpayload/configs/defconfig
@@ -78,6 +78,7 @@ CONFIG_LP_USB_HID=y
CONFIG_LP_USB_HUB=y
CONFIG_LP_USB_MSC=y
CONFIG_LP_USB_GEN_HUB=y
+# CONFIG_LP_USB_DWC2 is not set
CONFIG_LP_USB_PCI=y
# CONFIG_LP_BIG_ENDIAN is not set
CONFIG_LP_LITTLE_ENDIAN=y
diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm
index ff2225f..750c0bd 100644
--- a/payloads/libpayload/configs/defconfig-arm
+++ b/payloads/libpayload/configs/defconfig-arm
@@ -71,6 +71,7 @@ CONFIG_LP_USB_HID=y
CONFIG_LP_USB_HUB=y
CONFIG_LP_USB_MSC=y
CONFIG_LP_USB_GEN_HUB=y
+# CONFIG_LP_USB_DWC2 is not set
# CONFIG_LP_USB_PCI is not set
# CONFIG_LP_BIG_ENDIAN is not set
CONFIG_LP_LITTLE_ENDIAN=y
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
index f3b147d..4aa71d3 100644
--- a/payloads/libpayload/drivers/Makefile.inc
+++ b/payloads/libpayload/drivers/Makefile.inc
@@ -100,6 +100,8 @@ libc-$(CONFIG_LP_USB_XHCI) += usb/xhci_commands.c
libc-$(CONFIG_LP_USB_XHCI) += usb/xhci_rh.c
libc-$(CONFIG_LP_USB_HID) += usb/usbhid.c
libc-$(CONFIG_LP_USB_MSC) += usb/usbmsc.c
+libc-$(CONFIG_LP_USB_DWC2) += usb/dwc2.c
+libc-$(CONFIG_LP_USB_DWC2) += usb/dwc2_rh.c
# used by both USB HID and keyboard
libc-y += hid.c
diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
new file mode 100644
index 0000000..1092cb4
--- /dev/null
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -0,0 +1,356 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Rockchip Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <libpayload.h>
+#include <arch/cache.h>
+
+#include "dwc2.h"
+#include "dwc2_private.h"
+
+static void dummy(hci_t *controller)
+{
+}
+
+static void dwc2_reinit(hci_t *controller)
+{
+ dwc2_reg_t *reg = DWC2_REG(controller);
+ gusbcfg_t gusbcfg = { .d32 = 0 };
+ grstctl_t grstctl = { .d32 = 0 };
+ gintsts_t gintsts = { .d32 = 0 };
+ gahbcfg_t gahbcfg = { .d32 = 0 };
+ grxfsiz_t grxfsiz = { .d32 = 0 };
+ hcintmsk_t hcintmsk = { .d32 = 0 };
+ gnptxfsiz_t gnptxfsiz = { .d32 = 0 };
+
+ const int timeout = 10000;
+ int i;
+
+ /* Wait for AHB idle */
+ for (i = 0; i < timeout; i++) {
+ udelay(1);
+ grstctl.d32 = readl(®->core.grstctl);
+ if (grstctl.ahbidle)
+ break;
+ }
+ if (i == timeout)
+ fatal("DWC2 Init error AHB Idle\n");
+
+ /* Restart the Phy Clock */
+ writel(0x0, ®->pcgr.pcgcctl);
+ /* Core soft reset */
+ grstctl.csftrst = 1;
+ writel(grstctl.d32, ®->core.grstctl);
+ for (i = 0; i < timeout; i++) {
+ udelay(1);
+ grstctl.d32 = readl(®->core.grstctl);
+ if (!grstctl.csftrst)
+ break;
+ }
+ if (i == timeout)
+ fatal("DWC2 Init error reset fail\n");
+
+ /* Set 16bit PHY if & Force host mode */
+ gusbcfg.d32 = readl(®->core.gusbcfg);
+ gusbcfg.phyif = 1;
+ gusbcfg.forcehstmode = 1;
+ gusbcfg.forcedevmode = 0;
+ writel(gusbcfg.d32, ®->core.gusbcfg);
+ /* Wait for force host mode effect, it may takes 100ms */
+ for (i = 0; i < timeout; i++) {
+ udelay(10);
+ gintsts.d32 = readl(®->core.gintsts);
+ if (gintsts.curmod)
+ break;
+ }
+ if (i == timeout)
+ fatal("DWC2 Init error force host mode fail\n");
+
+ /*
+ * Config FIFO
+ * The non-periodic tx fifo and rx fifo share one continuous
+ * piece of IP-internal SRAM.
+ */
+ grxfsiz.rxfdep = DWC2_RXFIFO_DEPTH;
+ writel(grxfsiz.d32, ®->core.grxfsiz);
+ gnptxfsiz.nptxfstaddr = DWC2_RXFIFO_DEPTH;
+ gnptxfsiz.nptxfdep = DWC2_NPTXFIFO_DEPTH;
+ writel(gnptxfsiz.d32, ®->core.gnptxfsiz);
+
+ /* Init host channels */
+ hcintmsk.xfercomp = 1;
+ hcintmsk.xacterr = 1;
+ hcintmsk.stall = 1;
+ hcintmsk.chhltd = 1;
+ hcintmsk.bblerr = 1;
+ for (i = 0; i < MAX_EPS_CHANNELS; i++)
+ writel(hcintmsk.d32, ®->host.hchn[i].hcintmaskn);
+
+ /* Unmask interrupt and configure DMA mode */
+ gahbcfg.glblintrmsk = 1;
+ gahbcfg.hbstlen = DMA_BURST_INCR8;
+ gahbcfg.dmaen = 1;
+ writel(gahbcfg.d32, ®->core.gahbcfg);
+
+ DWC2_INST(controller)->hprt0 = ®->host.hprt;
+
+ usb_debug("DWC2 init finished!\n");
+}
+
+static void dwc2_shutdown(hci_t *controller)
+{
+ detach_controller(controller);
+ free(DWC2_INST(controller)->dma_buffer);
+ free(DWC2_INST(controller));
+ free(controller);
+}
+
+/*
+ * This function returns the actual transfer length when the transfer succeeded
+ * or an error code if the transfer failed
+ */
+static int
+wait_for_complete(endpoint_t *ep, uint32_t ch_num)
+{
+ hcint_t hcint;
+ hcchar_t hcchar;
+ hctsiz_t hctsiz;
+ dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
+ int timeout = 600000; /* time out after 600000 * 5us == 3s */
+
+ /*
+ * TODO: We should take care of up to three times of transfer error
+ * retry here, according to the USB 2.0 spec 4.5.2
+ */
+ do {
+ udelay(5);
+ hcint.d32 = readl(®->host.hchn[ch_num].hcintn);
+ hctsiz.d32 = readl(®->host.hchn[ch_num].hctsizn);
+
+ if (hcint.chhltd) {
+ writel(hcint.d32, ®->host.hchn[ch_num].hcintn);
+
+ if (hcint.xfercomp)
+ return hctsiz.xfersize;
+ else if (hcint.xacterr)
+ return -HCSTAT_XFERERR;
+ else if (hcint.bblerr)
+ return -HCSTAT_BABBLE;
+ else if (hcint.stall)
+ return -HCSTAT_STALL;
+ else
+ return -HCSTAT_UNKNOW;
+ }
+ } while (timeout--);
+
+ /* Release the channel on timeout */
+ hcchar.d32 = readl(®->host.hchn[ch_num].hccharn);
+ if (hcchar.chen) {
+ /*
+ * Programming the HCCHARn register with the chdis and
+ * chena bits set to 1 at the same time to disable the
+ * channel and the core will generate a channel halted
+ * interrupt.
+ */
+ hcchar.chdis = 1;
+ writel(hcchar.d32, ®->host.hchn[ch_num].hccharn);
+ do {
+ hcchar.d32 = readl(®->host.hchn[ch_num].hccharn);
+ } while (hcchar.chen);
+
+ }
+
+ /* Clear all pending interrupt flags */
+ hcint.d32 = ~0;
+ writel(hcint.d32, ®->host.hchn[ch_num].hcintn);
+
+ return -HCSTAT_TIMEOUT;
+}
+
+static int
+dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
+ uint32_t ch_num, u8 *data_buf)
+{
+ uint32_t do_copy;
+ int ret;
+ uint32_t packet_cnt;
+ uint32_t packet_size;
+ uint32_t transferred = 0;
+ uint32_t inpkt_length;
+ hctsiz_t hctsiz = { .d32 = 0 };
+ hcchar_t hcchar = { .d32 = 0 };
+ void *aligned_buf;
+ dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
+
+ packet_size = ep->maxpacketsize;
+ packet_cnt = ALIGN_UP(size, packet_size) / packet_size;
+ inpkt_length = packet_cnt * packet_size;
+ /* At least 1 packet should be programed */
+ packet_cnt = (packet_cnt == 0) ? 1 : packet_cnt;
+
+ /*
+ * For an IN, this field is the buffer size that the application has
+ * reserved for the transfer. The application should program this field
+ * as integer multiple of the maximum packet size for IN transactions.
+ */
+ hctsiz.xfersize = (dir == EPDIR_OUT) ? size : inpkt_length;
+ hctsiz.pktcnt = packet_cnt;
+ hctsiz.pid = pid;
+
+ hcchar.mps = packet_size;
+ hcchar.epnum = ep->endpoint & 0xf;
+ hcchar.epdir = dir;
+ hcchar.eptype = ep->type;
+ hcchar.multicnt = 1;
+ hcchar.devaddr = ep->dev->address;
+ hcchar.chdis = 0;
+ hcchar.chen = 1;
+
+ if (size > DMA_SIZE) {
+ usb_debug("Transfer too large: %d\n", size);
+ return -1;
+ }
+
+ /*
+ * Check the buffer address which should be 4-byte aligned and DMA
+ * coherent
+ */
+ do_copy = !dma_coherent(data_buf) || ((uintptr_t)data_buf & 0x3);
+ aligned_buf = do_copy ? DWC2_INST(ep->dev->controller)->dma_buffer :
+ data_buf;
+
+ if (do_copy && (dir == EPDIR_OUT))
+ memcpy(aligned_buf, data_buf, size);
+
+ writel(hctsiz.d32, ®->host.hchn[ch_num].hctsizn);
+ writel((uint32_t)aligned_buf, ®->host.hchn[ch_num].hcdman);
+ writel(hcchar.d32, ®->host.hchn[ch_num].hccharn);
+
+ ret = wait_for_complete(ep, ch_num);
+
+ if (ret >= 0) {
+ /* Calculate actual transferred length */
+ transferred = (dir == EPDIR_IN) ? inpkt_length - ret : ret;
+
+ if (do_copy && (dir == EPDIR_IN))
+ memcpy(data_buf, aligned_buf, transferred);
+ }
+
+ /* Save data toggle */
+ hctsiz.d32 = readl(®->host.hchn[ch_num].hctsizn);
+ ep->toggle = hctsiz.pid;
+
+ if (ret < 0) {
+ usb_debug("%s Transfer stop code: %x\n", __func__, ret);
+ return ret;
+ }
+ return transferred;
+}
+
+static int
+dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
+{
+ ep_dir_t data_dir;
+
+ if (ep->direction == IN)
+ data_dir = EPDIR_IN;
+ else if (ep->direction == OUT)
+ data_dir = EPDIR_OUT;
+ else
+ return -1;
+
+ return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src);
+}
+
+static int
+dwc2_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
+ int dalen, u8 *src)
+{
+ int ret = 0;
+
+ ep_dir_t data_dir;
+
+ if (dir == IN)
+ data_dir = EPDIR_IN;
+ else if (dir == OUT)
+ data_dir = EPDIR_OUT;
+ else
+ return -1;
+
+ /* Setup Phase */
+ if (dwc2_transfer(&dev->endpoints[0], drlen, PID_SETUP, EPDIR_OUT, 0,
+ setup) < 0)
+ return -1;
+ /* Data Phase */
+ if (dalen > 0) {
+ ret = dwc2_transfer(&dev->endpoints[0], dalen, PID_DATA1,
+ data_dir, 0, src);
+ if (ret < 0)
+ return -1;
+ }
+ /* Status Phase */
+ if (dwc2_transfer(&dev->endpoints[0], 0, PID_DATA1, !data_dir, 0,
+ NULL) < 0)
+ return -1;
+
+ return ret;
+}
+
+hci_t *dwc2_init(void *bar)
+{
+ hci_t *controller = new_controller();
+ controller->instance = xzalloc(sizeof(dwc_ctrl_t));
+
+ DWC2_INST(controller)->dma_buffer = dma_malloc(DMA_SIZE);
+ if (!DWC2_INST(controller)->dma_buffer) {
+ usb_debug("Not enough DMA memory for DWC2 bounce buffer\n");
+ goto free_dwc2;
+ }
+
+ controller->type = DWC2;
+ controller->start = dummy;
+ controller->stop = dummy;
+ controller->reset = dummy;
+ controller->init = dwc2_reinit;
+ controller->shutdown = dwc2_shutdown;
+ controller->bulk = dwc2_bulk;
+ controller->control = dwc2_control;
+ controller->set_address = generic_set_address;
+ controller->finish_device_config = NULL;
+ controller->destroy_device = NULL;
+ controller->create_intr_queue = NULL;
+ controller->destroy_intr_queue = NULL;
+ controller->poll_intr_queue = NULL;
+ controller->reg_base = (uintptr_t)bar;
+ init_device_entry(controller, 0);
+
+ /* Init controller */
+ controller->init(controller);
+
+ /* Setup up root hub */
+ controller->devices[0]->controller = controller;
+ controller->devices[0]->init = dwc2_rh_init;
+ controller->devices[0]->init(controller->devices[0]);
+ return controller;
+
+free_dwc2:
+ detach_controller(controller);
+ free(DWC2_INST(controller));
+ free(controller);
+ return NULL;
+}
diff --git a/payloads/libpayload/drivers/usb/dwc2.h b/payloads/libpayload/drivers/usb/dwc2.h
new file mode 100644
index 0000000..e9ca39d
--- /dev/null
+++ b/payloads/libpayload/drivers/usb/dwc2.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Rockchip Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __DWC2_HCD_H__
+#define __DWC2_HCD_H__
+#include <usb/usb.h>
+
+hci_t *dwc2_init(void *bar);
+void dwc2_rh_init (usbdev_t *dev);
+
+#endif
diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h
new file mode 100644
index 0000000..9bd8376
--- /dev/null
+++ b/payloads/libpayload/drivers/usb/dwc2_private.h
@@ -0,0 +1,643 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Rockchip Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __DWC2_REGS_H__
+#define __DWC2_REGS_H__
+#define MAX_EPS_CHANNELS 16
+
+typedef struct core_reg {
+ uint32_t gotgctl;
+ uint32_t gotgint;
+ uint32_t gahbcfg;
+ uint32_t gusbcfg;
+ uint32_t grstctl;
+ uint32_t gintsts;
+ uint32_t gintmsk;
+ uint32_t grxstsr;
+ uint32_t grxstsp;
+ uint32_t grxfsiz;
+ uint32_t gnptxfsiz;
+ uint32_t gnptxsts;
+ uint32_t gi2cctl;
+ uint32_t gpvndctl;
+ uint32_t ggpio;
+ uint32_t guid;
+ uint32_t gsnpsid;
+ uint32_t ghwcfg1;
+ uint32_t ghwcfg2;
+ uint32_t ghwcfg3;
+ uint32_t ghwcfg4;
+ uint32_t reserved1[(0x100 - 0x54) / 4];
+ uint32_t hptxfsiz;
+ uint32_t dptxfsiz_dieptxf[15];
+ uint32_t reserved2[(0x400 - 0x140) / 4];
+} core_reg_t;
+
+typedef struct hc_reg {
+ uint32_t hccharn;
+ uint32_t hcspltn;
+ uint32_t hcintn;
+ uint32_t hcintmaskn;
+ uint32_t hctsizn;
+ uint32_t hcdman;
+ uint32_t reserved[2];
+} hc_reg_t;
+
+/* Host Mode Register Structures */
+typedef struct host_reg {
+ uint32_t hcfg;
+ uint32_t hfir;
+ uint32_t hfnum;
+ uint32_t reserved0;
+ uint32_t hptxsts;
+ uint32_t haint;
+ uint32_t haintmsk;
+ uint32_t reserved1[(0x440 - 0x41c) / 4];
+ uint32_t hprt;
+ uint32_t reserved2[(0x500 - 0x444) / 4];
+ hc_reg_t hchn[MAX_EPS_CHANNELS];
+ uint32_t reserved3[(0x800 - 0x700) / 4];
+} host_reg_t;
+
+/* Device IN ep reg */
+typedef struct in_ep_reg {
+ uint32_t diepctl;
+ uint32_t reserved04;
+ uint32_t diepint;
+ uint32_t reserved0c;
+ uint32_t dieptsiz;
+ uint32_t diepdma;
+ uint32_t dtxfsts;
+ uint32_t diepdmab;
+} in_ep_reg_t;
+
+typedef struct out_ep_reg {
+ uint32_t doepctl;
+ uint32_t reserved04;
+ uint32_t doepint;
+ uint32_t reserved0c;
+ uint32_t doeptsiz;
+ uint32_t doepdma;
+ uint32_t reserved18;
+ uint32_t doepdmab;
+} out_ep_reg_t;
+
+/* Device Mode Registers Structures */
+typedef struct device_reg {
+ uint32_t dcfg;
+ uint32_t dctl;
+ uint32_t dsts;
+ uint32_t unused;
+ uint32_t diepmsk;
+ uint32_t doepmsk;
+ uint32_t daint;
+ uint32_t daintmsk;
+ uint32_t dtknqr1;
+ uint32_t dtknqr2;
+ uint32_t dvbusdis;
+ uint32_t dvbuspulse;
+ uint32_t dtknqr3_dthrctl;
+ uint32_t dtknqr4_fifoemptymsk;
+ uint32_t reserved1[(0x900 - 0x838) / 4];
+
+ in_ep_reg_t inep[MAX_EPS_CHANNELS];
+ out_ep_reg_t outep[MAX_EPS_CHANNELS];
+ uint32_t reserved8[(0xe00 - 0xd00) / 4];
+} device_reg_t;
+
+typedef struct pwr_clk_ctrl_reg {
+ uint32_t pcgcctl;
+ uint32_t reserved[(0x1000 - 0xe04) / 4];
+} pwr_clk_ctrl_reg_t;
+
+typedef struct data_fifo {
+ uint32_t dataport;
+ uint32_t reserved[(0x1000 - 0x004) / 4];
+} data_fifo_t;
+
+typedef struct dwc2_otg_reg {
+ core_reg_t core;
+ host_reg_t host;
+ device_reg_t device;
+ pwr_clk_ctrl_reg_t pcgr;
+ data_fifo_t dfifo[MAX_EPS_CHANNELS];
+ uint32_t reserved[(0x40000 - 0x11000) / 4];
+} dwc2_reg_t;
+
+/**
+ * This union represents the bit fields of the Core AHB Configuration
+ * Register (GAHBCFG).
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ unsigned glblintrmsk:1;
+#define GLBINT_ENABLE 1
+
+ unsigned hbstlen:4;
+#define DMA_BURST_SINGLE 0
+#define DMA_BURST_INCR 1
+#define DMA_BURST_INCR4 3
+#define DMA_BURST_INCR8 5
+#define DMA_BURST_INCR16 7
+
+ unsigned dmaen:1;
+ unsigned reserved:1;
+ unsigned nptxfemplvl:1;
+ unsigned ptxfemplvl:1;
+ unsigned reserved9_31:23;
+ };
+} gahbcfg_t;
+
+/**
+ * This union represents the bit fields of the Core USB Configuration
+ * Register (GUSBCFG).
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ unsigned toutcal:3;
+ unsigned phyif:1;
+ unsigned ulpiutmisel:1;
+ unsigned fsintf:1;
+ unsigned physel:1;
+ unsigned ddrsel:1;
+ unsigned srpcap:1;
+ unsigned hnpcap:1;
+ unsigned usbtrdtim:4;
+ unsigned reserved14:1;
+ unsigned phylpwrclksel:1;
+ unsigned otgi2csel:1;
+ unsigned ulpifsls:1;
+ unsigned ulpiautores:1;
+ unsigned ulpiclksusm:1;
+ unsigned ulpiextvbusdrv:1;
+ unsigned ulpiextvbusindicator:1;
+ unsigned termseldlpulse:1;
+ unsigned reserved23_28:6;
+ unsigned forcehstmode:1;
+ unsigned forcedevmode:1;
+ unsigned cortxpkt:1;
+ };
+} gusbcfg_t;
+
+/**
+ * This union represents the bit fields of the Core Reset Register
+ * (GRSTCTL).
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ /** Core Soft Reset (CSftRst) (Device and Host)
+ *
+ * The application can flush the control logic in the
+ * entire core using this bit. This bit resets the
+ * pipelines in the AHB Clock domain as well as the
+ * PHY Clock domain.
+ *
+ * The state machines are reset to an IDLE state, the
+ * control bits in the CSRs are cleared, all the
+ * transmit FIFOs and the receive FIFO are flushed.
+ *
+ * The status mask bits that control the generation of
+ * the interrupt, are cleared, to clear the
+ * interrupt. The interrupt status bits are not
+ * cleared, so the application can get the status of
+ * any events that occurred in the core after it has
+ * set this bit.
+ *
+ * Any transactions on the AHB are terminated as soon
+ * as possible following the protocol. Any
+ * transactions on the USB are terminated immediately.
+ *
+ * The configuration settings in the CSRs are
+ * unchanged, so the software doesn't have to
+ * reprogram these registers (Device
+ * Configuration/Host Configuration/Core System
+ * Configuration/Core PHY Configuration).
+ *
+ * The application can write to this bit, any time it
+ * wants to reset the core. This is a self clearing
+ * bit and the core clears this bit after all the
+ * necessary logic is reset in the core, which may
+ * take several clocks, depending on the current state
+ * of the core.
+ */
+ unsigned csftrst:1;
+ /** Hclk Soft Reset
+ *
+ * The application uses this bit to reset the control logic in
+ * the AHB clock domain. Only AHB clock domain pipelines are
+ * reset.
+ */
+ unsigned hsftrst:1;
+ /** Host Frame Counter Reset (Host Only)<br>
+ *
+ * The application can reset the (micro)frame number
+ * counter inside the core, using this bit. When the
+ * (micro)frame counter is reset, the subsequent SOF
+ * sent out by the core, will have a (micro)frame
+ * number of 0.
+ */
+ unsigned frmcntrrst:1;
+ /** In Token Sequence Learning Queue Flush
+ * (INTknQFlsh) (Device Only)
+ */
+ unsigned intknqflsh:1;
+ /** RxFIFO Flush (RxFFlsh) (Device and Host)
+ *
+ * The application can flush the entire Receive FIFO
+ * using this bit. <p>The application must first
+ * ensure that the core is not in the middle of a
+ * transaction. <p>The application should write into
+ * this bit, only after making sure that neither the
+ * DMA engine is reading from the RxFIFO nor the MAC
+ * is writing the data in to the FIFO. <p>The
+ * application should wait until the bit is cleared
+ * before performing any other operations. This bit
+ * will takes 8 clocks (slowest of PHY or AHB clock)
+ * to clear.
+ */
+ unsigned rxfflsh:1;
+ /** TxFIFO Flush (TxFFlsh) (Device and Host).
+ *
+ * This bit is used to selectively flush a single or
+ * all transmit FIFOs. The application must first
+ * ensure that the core is not in the middle of a
+ * transaction. <p>The application should write into
+ * this bit, only after making sure that neither the
+ * DMA engine is writing into the TxFIFO nor the MAC
+ * is reading the data out of the FIFO. <p>The
+ * application should wait until the core clears this
+ * bit, before performing any operations. This bit
+ * will takes 8 clocks (slowest of PHY or AHB clock)
+ * to clear.
+ */
+ unsigned txfflsh:1;
+
+ /** TxFIFO Number (TxFNum) (Device and Host).
+ *
+ * This is the FIFO number which needs to be flushed,
+ * using the TxFIFO Flush bit. This field should not
+ * be changed until the TxFIFO Flush bit is cleared by
+ * the core.
+ * - 0x0 : Non Periodic TxFIFO Flush
+ * - 0x1 : Periodic TxFIFO #1 Flush in device mode
+ * or Periodic TxFIFO in host mode
+ * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
+ * - ...
+ * - 0xF : Periodic TxFIFO #15 Flush in device mode
+ * - 0x10: Flush all the Transmit NonPeriodic and
+ * Transmit Periodic FIFOs in the core
+ */
+ unsigned txfnum:5;
+ /** Reserved */
+ unsigned reserved11_29:19;
+ /** DMA Request Signal. Indicated DMA request is in
+ * probress. Used for debug purpose. */
+ unsigned dmareq:1;
+ /** AHB Master Idle. Indicates the AHB Master State
+ * Machine is in IDLE condition. */
+ unsigned ahbidle:1;
+ } ;
+} grstctl_t;
+
+/**
+ * This union represents the bit fields of the Core Interrupt Mask
+ * Register (GINTMSK).
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ unsigned curmod:1;
+ unsigned modemis:1;
+ unsigned otgint:1;
+ unsigned sof:1;
+ unsigned rxflvl:1;
+ unsigned nptxfemp:1;
+ unsigned ginnakeff:1;
+ unsigned goutnakeff:1;
+ unsigned reserved8:1;
+ unsigned i2cint:1;
+ unsigned erlysusp:1;
+ unsigned usbsusp:1;
+ unsigned usbrst:1;
+ unsigned enumdone:1;
+ unsigned isooutdrop:1;
+ unsigned eopf:1;
+ unsigned reserved16_20:5;
+ unsigned incompip:1;
+ unsigned reserved22_23:2;
+ unsigned prtint:1;
+ unsigned hchint:1;
+ unsigned ptxfemp:1;
+ unsigned reserved27:1;
+ unsigned conidstschng:1;
+ unsigned disconnint:1;
+ unsigned sessreqint:1;
+ unsigned wkupint:1;
+ } ;
+} gintmsk_t;
+
+/**
+* This union represents the bit fields of the Core Non-Periodic
+* Transmit FIFO Size Register(GNPTXFSIZ).
+*/
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ unsigned nptxfstaddr:16;
+ unsigned nptxfdep:16;
+#define DWC2_NPTXFIFO_DEPTH 0x80
+ };
+} gnptxfsiz_t;
+
+/**
+ * This union represents the bit fields of the Core Receive FIFO Size
+ * Register(GRXFSIZ).
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ /*The value in this fieles is in terms of 32-bit words size.
+ */
+ struct {
+ unsigned rxfdep:16;
+#define DWC2_RXFIFO_DEPTH 0x200
+ unsigned reserved:16;
+ };
+} grxfsiz_t;
+
+/**
+ * This union represents the bit fields of the Core Interrupt Register
+ * (GINTSTS).
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+#define SOF_INTR_MASK 0x0008
+ /* register bits */
+ struct {
+ unsigned curmod:1;
+#define HOST_MODE 1
+#define DEVICE_MODE 0
+ unsigned modemis:1;
+ unsigned otgint:1;
+ unsigned sof:1;
+ unsigned rxflvl:1;
+ unsigned nptxfemp:1;
+ unsigned ginnakeff:1;
+ unsigned goutnakeff:1;
+ unsigned reserved8:1;
+ unsigned i2cint:1;
+ unsigned erlysusp:1;
+ unsigned usbsusp:1;
+ unsigned usbrst:1;
+ unsigned enumdone:1;
+ unsigned isooutdrop:1;
+ unsigned eopf:1;
+ unsigned reserved16_20:5;
+ unsigned incompip:1;
+ unsigned reserved22_23:2;
+ unsigned prtint:1;
+ unsigned hchint:1;
+ unsigned ptxfemp:1;
+ unsigned reserved27:1;
+ unsigned conidstschng:1;
+ unsigned disconnint:1;
+ unsigned sessreqint:1;
+ unsigned wkupint:1;
+ };
+} gintsts_t;
+
+/**
+ * This union represents the bit fields in the Host Configuration Register.
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+
+ /* register bits */
+ struct {
+ /** FS/LS Phy Clock Select */
+ unsigned fslspclksel:2;
+#define PHYCLK_30_60_MHZ 0
+#define PHYCLK_48_MHZ 1
+#define PHYCLK_6_MHZ 2
+
+ /** FS/LS Only Support */
+ unsigned fslssupp:1;
+ };
+} hcfg_t;
+
+/**
+ * This union represents the bit fields in the Host Port Control and status
+ * Register.
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ unsigned prtconnsts:1;
+ unsigned prtconndet:1;
+ unsigned prtena:1;
+ unsigned prtenchng:1;
+ unsigned prtovrcurract:1;
+ unsigned prtovrcurrchng:1;
+ unsigned prtres:1;
+ unsigned prtsusp:1;
+ unsigned prtrst:1;
+ unsigned reserved9:1;
+ unsigned prtlnsts:2;
+ unsigned prtpwr:1;
+ unsigned prttstctl:4;
+ unsigned prtspd:2;
+#define PRTSPD_HIGH 0
+#define PRTSPD_FULL 1
+#define PRTSPD_LOW 2
+ unsigned reserved19_31:13;
+ };
+} hprt_t;
+/* Mask W1C bits */
+#define HPRT_W1C_MASK (~((1 << 1) | (1 << 2) | (1 << 3) | (1 << 5)))
+
+/**
+ * This union represents the bit fields in the Host Channel Characteristics
+ * Register.
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+
+ /* register bits */
+ struct {
+ /** Maximum packet size in bytes */
+ unsigned mps:11;
+ /** Endpoint number */
+ unsigned epnum:4;
+ /** 0: OUT, 1: IN */
+ unsigned epdir:1;
+ unsigned reserved:1;
+ /** 0: Full/high speed device, 1: Low speed device */
+ unsigned lspddev:1;
+ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
+ unsigned eptype:2;
+ /** Packets per frame for periodic transfers. 0 is reserved. */
+ unsigned multicnt:2;
+ /** Device address */
+ unsigned devaddr:7;
+ /**
+ * Frame to transmit periodic transaction.
+ * 0: even, 1: odd
+ */
+ unsigned oddfrm:1;
+ /** Channel disable */
+ unsigned chdis:1;
+ /** Channel enable */
+ unsigned chen:1;
+ };
+} hcchar_t;
+
+typedef enum {
+ EPDIR_OUT = 0,
+ EPDIR_IN,
+} ep_dir_t;
+
+/**
+ * This union represents the bit fields in the Host All Interrupt
+ * Register.
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ /** Transfer Complete */
+ unsigned xfercomp:1;
+ /** Channel Halted */
+ unsigned chhltd:1;
+ /** AHB Error */
+ unsigned ahberr:1;
+ /** STALL Response Received */
+ unsigned stall:1;
+ /** NAK Response Received */
+ unsigned nak:1;
+ /** ACK Response Received */
+ unsigned ack:1;
+ /** NYET Response Received */
+ unsigned nyet:1;
+ /** Transaction Err */
+ unsigned xacterr:1;
+ /** Babble Error */
+ unsigned bblerr:1;
+ /** Frame Overrun */
+ unsigned frmovrun:1;
+ /** Data Toggle Error */
+ unsigned datatglerr:1;
+ /** Reserved */
+ unsigned reserved:21;
+ };
+} hcint_t;
+
+/**
+ * This union represents the bit fields in the Host Channel Transfer Size
+ * Register.
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+
+ /* register bits */
+ struct {
+ /* Total transfer size in bytes */
+ unsigned xfersize:19;
+ /** Data packets to transfer */
+ unsigned pktcnt:10;
+ /**
+ * Packet ID for next data packet
+ * 0: DATA0
+ * 1: DATA2
+ * 2: DATA1
+ * 3: MDATA (non-Control), SETUP (Control)
+ */
+ unsigned pid:2;
+#define PID_DATA0 0
+#define PID_DATA1 2
+#define PID_DATA2 1
+#define PID_MDATA 3
+#define PID_SETUP 3
+ /* Do PING protocol when 1 */
+ unsigned dopng:1;
+ };
+} hctsiz_t;
+
+/**
+ * This union represents the bit fields in the Host Channel Interrupt Mask
+ * Register.
+ */
+typedef union {
+ /* raw register data */
+ uint32_t d32;
+ /* register bits */
+ struct {
+ unsigned xfercomp:1;
+ unsigned chhltd:1;
+ unsigned ahberr:1;
+ unsigned stall:1;
+ unsigned nak:1;
+ unsigned ack:1;
+ unsigned nyet:1;
+ unsigned xacterr:1;
+ unsigned bblerr:1;
+ unsigned frmovrun:1;
+ unsigned datatglerr:1;
+ unsigned reserved:21;
+ };
+} hcintmsk_t;
+
+typedef struct dwc_ctrl {
+#define DMA_SIZE (64 * 1024)
+ void *dma_buffer;
+ uint32_t *hprt0;
+} dwc_ctrl_t;
+
+#define DWC2_INST(controller) ((dwc_ctrl_t *)((controller)->instance))
+#define DWC2_REG(controller) ((dwc2_reg_t *)((controller)->reg_base))
+
+typedef enum {
+ HCSTAT_DONE = 0,
+ HCSTAT_XFERERR,
+ HCSTAT_BABBLE,
+ HCSTAT_STALL,
+ HCSTAT_UNKNOW,
+ HCSTAT_TIMEOUT,
+} hcstat_t;
+#endif
diff --git a/payloads/libpayload/drivers/usb/dwc2_rh.c b/payloads/libpayload/drivers/usb/dwc2_rh.c
new file mode 100644
index 0000000..3dd5042
--- /dev/null
+++ b/payloads/libpayload/drivers/usb/dwc2_rh.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Rockchip Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <usb/usb.h>
+#include "generic_hub.h"
+#include "dwc2_private.h"
+#include "dwc2.h"
+
+static int
+dwc2_rh_port_status_changed(usbdev_t *const dev, const int port)
+{
+ hprt_t hprt;
+ int changed;
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ hprt.d32 = readl(dwc2->hprt0);
+ changed = hprt.prtconndet;
+
+ /* Clear connect detect flag */
+ if (changed) {
+ hprt.d32 &= HPRT_W1C_MASK;
+ hprt.prtconndet = 1;
+ writel(hprt.d32, dwc2->hprt0);
+ }
+ return changed;
+}
+
+static int
+dwc2_rh_port_connected(usbdev_t *const dev, const int port)
+{
+ hprt_t hprt;
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ hprt.d32 = readl(dwc2->hprt0);
+ return hprt.prtconnsts;
+}
+
+static int
+dwc2_rh_port_in_reset(usbdev_t *const dev, const int port)
+{
+ hprt_t hprt;
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ hprt.d32 = readl(dwc2->hprt0);
+ return hprt.prtrst;
+}
+
+static int
+dwc2_rh_port_enabled(usbdev_t *const dev, const int port)
+{
+ hprt_t hprt;
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ hprt.d32 = readl(dwc2->hprt0);
+ return hprt.prtena;
+}
+
+static usb_speed
+dwc2_rh_port_speed(usbdev_t *const dev, const int port)
+{
+ hprt_t hprt;
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ hprt.d32 = readl(dwc2->hprt0);
+ if (hprt.prtena) {
+ switch (hprt.prtspd) {
+ case PRTSPD_HIGH:
+ return HIGH_SPEED;
+ case PRTSPD_FULL:
+ return FULL_SPEED;
+ case PRTSPD_LOW:
+ return LOW_SPEED;
+ }
+ }
+ return -1;
+}
+
+static int
+dwc2_rh_reset_port(usbdev_t *const dev, const int port)
+{
+ hprt_t hprt;
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ hprt.d32 = readl(dwc2->hprt0);
+ hprt.d32 &= HPRT_W1C_MASK;
+ hprt.prtrst = 1;
+ writel(hprt.d32, dwc2->hprt0);
+
+ /* Wait a bit while reset is active. */
+ mdelay(50);
+
+ /* Deassert reset. */
+ hprt.prtrst = 0;
+ writel(hprt.d32, dwc2->hprt0);
+
+ /*
+ * If reset and speed enum success the DWC2 core will set enable bit
+ * after port reset bit is deasserted
+ */
+ mdelay(1);
+ hprt.d32 = readl(dwc2->hprt0);
+ usb_debug("%s reset port ok, hprt = 0x%08x\n", __func__, hprt.d32);
+
+ if (!hprt.prtena) {
+ usb_debug("%s enable port fail! hprt = 0x%08x\n",
+ __func__, hprt.d32);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int
+dwc2_rh_enable_port(usbdev_t *const dev, const int port)
+{
+ hprt_t hprt;
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ /* Power on the port */
+ hprt.d32 = readl(dwc2->hprt0);
+ hprt.d32 &= HPRT_W1C_MASK;
+ hprt.prtpwr = 1;
+ writel(hprt.d32, dwc2->hprt0);
+ return 0;
+}
+
+static int
+dwc2_rh_disable_port(usbdev_t *const dev, const int port)
+{
+ hprt_t hprt;
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ hprt.d32 = readl(dwc2->hprt0);
+ hprt.d32 &= HPRT_W1C_MASK;
+ /* Disable the port*/
+ hprt.prtena = 1;
+ /* Power off the port */
+ hprt.prtpwr = 0;
+ writel(hprt.d32, dwc2->hprt0);
+ return 0;
+}
+
+static const generic_hub_ops_t dwc2_rh_ops = {
+ .hub_status_changed = NULL,
+ .port_status_changed = dwc2_rh_port_status_changed,
+ .port_connected = dwc2_rh_port_connected,
+ .port_in_reset = dwc2_rh_port_in_reset,
+ .port_enabled = dwc2_rh_port_enabled,
+ .port_speed = dwc2_rh_port_speed,
+ .enable_port = dwc2_rh_enable_port,
+ .disable_port = dwc2_rh_disable_port,
+ .start_port_reset = NULL,
+ .reset_port = dwc2_rh_reset_port,
+};
+
+void
+dwc2_rh_init(usbdev_t *dev)
+{
+ dwc_ctrl_t *const dwc2 = DWC2_INST(dev->controller);
+
+ /* we can set them here because a root hub _really_ shouldn't
+ appear elsewhere */
+ dev->address = 0;
+ dev->hub = -1;
+ dev->port = -1;
+
+ generic_hub_init(dev, 1, &dwc2_rh_ops);
+ usb_debug("dwc2_rh_init HPRT 0x%08x p = %p\n ",
+ readl(dwc2->hprt0), dwc2->hprt0);
+ usb_debug("DWC2: root hub init done\n");
+}
diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c
index 4225c3f..7a5828d 100644
--- a/payloads/libpayload/drivers/usb/usbinit.c
+++ b/payloads/libpayload/drivers/usb/usbinit.c
@@ -34,6 +34,7 @@
#include "ohci.h"
#include "ehci.h"
#include "xhci.h"
+#include "dwc2.h"
#include <usb/usbdisk.h>
#ifdef CONFIG_LP_USB_PCI
@@ -182,6 +183,10 @@ hci_t *usb_add_mmio_hc(hc_type type, void *bar)
case EHCI:
return ehci_init((unsigned long)bar);
#endif
+#ifdef CONFIG_LP_USB_DWC2
+ case DWC2:
+ return dwc2_init(bar);
+#endif
#ifdef CONFIG_LP_USB_XHCI
case XHCI:
return xhci_init((unsigned long)bar);
diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h
index 4d8b2c2..df507db 100644
--- a/payloads/libpayload/include/usb/usb.h
+++ b/payloads/libpayload/include/usb/usb.h
@@ -207,7 +207,7 @@ struct usbdev {
void (*poll) (usbdev_t *dev);
};
-typedef enum { OHCI = 0, UHCI = 1, EHCI = 2, XHCI = 3} hc_type;
+typedef enum { OHCI = 0, UHCI = 1, EHCI = 2, XHCI = 3, DWC2 = 4} hc_type;
struct usbdev_hc {
hci_t *next;
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