[coreboot-gerrit] New patch to review for coreboot: 41db7da i945/gma: Fix wrong comment about the documentation.

[Denis Carikli (GNUtoo@no-log.org)]

Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9622

-gerrit

commit 41db7da86c0d2feb73d674a4c31a36cba18886ae
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date:   Tue Oct 14 07:33:53 2014 +0200

    i945/gma: Fix wrong comment about the documentation.
    
    The GTT location is is documented in the "309219" datasheet.
    For instance it can be found in the TOLUD register description.
    
    The 309219 datasheet is for the
    "Mobile Intel® 945 Express Chipset Family". It was published in 2008.
    
    Change-Id: I75ac095ebc577e031af566963ebffe9ed2587c96
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
 src/northbridge/intel/i945/gma.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index cee0640..e5974c9 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -58,12 +58,7 @@ static int gtt_setup(void *mmiobase)
 
 	/*
 	 * The Video BIOS places the GTT right below top of memory.
-	 *
-	 * It is not documented in the Intel 945 datasheet, but the Intel
-	 * developers said that it is normally placed there.
-	 *
-	 * TODO: Add option to make the GTT size runtime configurable
-	*/
+	 */
 	tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
 	PGETBL_save = tom - 256 * KiB;
 	PGETBL_save |= PGETBL_ENABLED;