[coreboot-gerrit] New patch to review for coreboot: 13f71ce CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstool
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Apr 13 21:21:14 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9619
-gerrit
commit 13f71ce6ea1949f738d05e9df5ea36d0c5f9bbb9
Author: Julius Werner <jwerner at chromium.org>
Date: Mon Nov 10 13:11:50 2014 -0800
CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstool
Some projects (like ChromeOS) put more content than described by CBFS
onto their image. For top-aligned images (read: x86), this has
traditionally been achieved with a CBFS_SIZE Kconfig (which denotes the
area actually managed by CBFS, as opposed to ROM_SIZE) that is used to
calculate the CBFS entry start offset. On bottom-aligned boards, many
define a fake (smaller) ROM_SIZE for only the CBFS part, which is not
consistently done and can be an issue because ROM_SIZE is expected to be
a power of two.
This patch changes all non-x86 boards to describe their actual
(physical) ROM size via one of the BOARD_ROMSIZE_KB_xxx options as a
mainboard Kconfig select (which is the correct place to declare
unchangeable physical properties of the board). It also changes the
cbfstool create invocation to use CBFS_SIZE as the -s parameter for
those architectures, which defaults to ROM_SIZE but gets overridden for
special use cases like ChromeOS. This has the advantage that cbfstool
has a consistent idea of where the area it is responsible for ends,
which offers better bounds-checking and is needed for a subsequent fix.
Also change the FMAP offset to default to right behind the (now
consistently known) CBFS region for non-x86 boards, which has emerged as
a de-facto standard on those architectures and allows us to reduce the
amount of custom configuration. In the future, the nightmare that is
ChromeOS's image build system could be redesigned to enforce this
automatically, and also confirm that it doesn't overwrite any space used
by CBFS (which is now consistently defined as the file size of
coreboot.rom on non-x86).
CQ-DEPEND=CL:231576,CL:231475
BRANCH=None
BUG=chromium:422501
TEST=Built and booted on Veyron_Pinky.
Change-Id: I89aa5b30e25679e074d4cb5eee4c08178892ada6
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: e707c67c69599274b890d0686522880aa2e16d71
Original-Change-Id: I4fce5a56a8d72f4c4dd3a08c129025f1565351cc
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229974
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
Makefile.inc | 7 +++++--
src/Kconfig | 8 +++++++-
src/arch/arm/Makefile.inc | 4 +++-
src/arch/arm64/Makefile.inc | 4 +++-
src/arch/mips/Makefile.inc | 5 +++--
src/arch/x86/Makefile.inc | 3 ++-
src/mainboard/google/cosmos/Kconfig | 2 +-
src/mainboard/google/nyan/Kconfig | 2 +-
src/mainboard/google/nyan_big/Kconfig | 2 +-
src/mainboard/google/nyan_blaze/Kconfig | 2 +-
src/mainboard/google/rush_ryu/Kconfig | 2 +-
src/mainboard/google/storm/Kconfig | 2 +-
src/mainboard/google/veyron_jerry/Kconfig | 2 +-
src/mainboard/google/veyron_mighty/Kconfig | 2 +-
src/vendorcode/google/chromeos/Kconfig | 1 +
15 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 10759f5..9c043c4 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -528,7 +528,7 @@ prebuild-files = \
prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
- $(CBFSTOOL) $@.tmp create -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
+ $(CBFSTOOL) $@.tmp create \
-B $(objcbfs)/bootblock.bin -a 64 \
$(CBFSTOOL_PRE1_OPTS)
$(prebuild-files) true
@@ -557,7 +557,10 @@ endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
- cp $(obj)/coreboot.pre $@.tmp
+# The full ROM may be larger than the CBFS part, so create an empty
+# file (filled with \377 = 0xff) and copy the CBFS image over it.
+ tr '\000' '\377' < /dev/zero 2> /dev/null | dd of=$@.tmp bs=8192 iflag=fullblock count=$$(($(CONFIG_ROM_SIZE) / 8192)) 2> /dev/null
+ dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null
$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
ifeq ($(CONFIG_PAYLOAD_NONE),y)
@printf " PAYLOAD none (as specified by user)\n"
diff --git a/src/Kconfig b/src/Kconfig
index 377f7cf..8a5d905 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -413,8 +413,14 @@ config IOAPIC
default n
config CBFS_SIZE
- hex
+ hex "Size of CBFS filesystem in ROM"
default ROM_SIZE
+ help
+ This is the part of the ROM actually managed by CBFS, located at the
+ end of the ROM (passed through cbfstool -o) on x86 and at at the start
+ of the ROM (passed through cbfstool -s) everywhere else. Defaults to
+ span the whole ROM but can be overwritten to make coreboot live
+ alongside other components (like ChromeOS's vboot/FMAP).
config CACHE_ROM_SIZE_OVERRIDE
hex
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 4277ca7..cfdb576 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -31,7 +31,9 @@ subdirs-y += armv4/ armv7/
###############################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y)
-CBFSTOOL_PRE1_OPTS = -m arm -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET)
+CBFSTOOL_PRE1_OPTS = -m arm -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \
+ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \
+ -o $(CONFIG_CBFS_ROM_OFFSET) -s $(CONFIG_CBFS_SIZE)
CBFSTOOL_PRE_OPTS = -b 0
endif
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index f81e76a..8e88d9c 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -34,7 +34,9 @@ subdirs-y += armv8/
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y)
-CBFSTOOL_PRE1_OPTS = -m arm64 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET)
+CBFSTOOL_PRE1_OPTS = -m arm64 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \
+ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \
+ -o $(CONFIG_CBFS_ROM_OFFSET) -s $(CONFIG_CBFS_SIZE)
endif
ifeq ($(CONFIG_ARCH_ARM64),y)
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index 0539c4f..ee88adf 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -24,8 +24,9 @@
###############################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y)
-CBFSTOOL_PRE1_OPTS = -m mips -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET)
-CBFSTOOL_PRE_OPTS = -b 0
+CBFSTOOL_PRE1_OPTS = -m mips -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \
+ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \
+ -o $(CONFIG_CBFS_ROM_OFFSET) -s $(CONFIG_CBFS_SIZE)
endif
###############################################################################
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3b3d26a..a2e68cc 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -61,7 +61,8 @@ mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE))
mbi.bin-type := mbi
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
-CBFSTOOL_PRE1_OPTS = -m x86 -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
+CBFSTOOL_PRE1_OPTS = -m x86 -s $(CONFIG_ROM_SIZE) \
+ -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
# Make sure that segment for .car.data is ignored while adding romstage.
CBFSTOOL_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt) -S ".car.data"
endif
diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig
index 0ebeae9..dc4a3b6 100644
--- a/src/mainboard/google/cosmos/Kconfig
+++ b/src/mainboard/google/cosmos/Kconfig
@@ -21,7 +21,7 @@ if BOARD_GOOGLE_COSMOS
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select BOARD_ROMSIZE_KB_1024
+ select BOARD_ROMSIZE_KB_2048
select BOARD_ID_SUPPORT
select CHROMEOS_VBNV_FLASH
select COMMON_CBFS_SPI_WRAPPER
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index 082985d..2f554ff 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select TEGRA124_MODEL_CD570M
select MAINBOARD_HAS_BOOTBLOCK_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
- select BOARD_ROMSIZE_KB_1024
+ select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
select VIRTUAL_DEV_SWITCH
diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
index 22958a9..6fc618a 100644
--- a/src/mainboard/google/nyan_big/Kconfig
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select TEGRA124_MODEL_CD570M
select MAINBOARD_HAS_BOOTBLOCK_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
- select BOARD_ROMSIZE_KB_1024
+ select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
select VIRTUAL_DEV_SWITCH
diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig
index 0902b4f..025cc6e 100644
--- a/src/mainboard/google/nyan_blaze/Kconfig
+++ b/src/mainboard/google/nyan_blaze/Kconfig
@@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_BOOTBLOCK_INIT
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_DO_NATIVE_VGA_INIT
- select BOARD_ROMSIZE_KB_1024
+ select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
select VIRTUAL_DEV_SWITCH
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig
index 6ba45e9..d6609e1 100644
--- a/src/mainboard/google/rush_ryu/Kconfig
+++ b/src/mainboard/google/rush_ryu/Kconfig
@@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_NVIDIA_TEGRA132
select MAINBOARD_DO_DSI_INIT
select MAINBOARD_HAS_BOOTBLOCK_INIT
- select BOARD_ROMSIZE_KB_4096
+ select BOARD_ROMSIZE_KB_8192
select VIRTUAL_DEV_SWITCH
select ARCH_SPINTABLE
diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig
index 00405e1..29f0a73 100644
--- a/src/mainboard/google/storm/Kconfig
+++ b/src/mainboard/google/storm/Kconfig
@@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_QC_IPQ806X
select BOARD_ID_SUPPORT
- select BOARD_ROMSIZE_KB_4096
+ select BOARD_ROMSIZE_KB_8192
select COMMON_CBFS_SPI_WRAPPER
select HAVE_HARD_RESET
select MAINBOARD_HAS_BOOTBLOCK_INIT
diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig
index 273b36e..b5aa2a4 100644
--- a/src/mainboard/google/veyron_jerry/Kconfig
+++ b/src/mainboard/google/veyron_jerry/Kconfig
@@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_ROCKCHIP_RK3288
select MAINBOARD_DO_NATIVE_VGA_INIT
select MAINBOARD_HAS_CHROMEOS
- select BOARD_ROMSIZE_KB_1024
+ select BOARD_ROMSIZE_KB_4096
select MAINBOARD_HAS_BOOTBLOCK_INIT
select HAVE_HARD_RESET
select RETURN_FROM_VERSTAGE
diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig
index 9a649bd..3436f88 100644
--- a/src/mainboard/google/veyron_mighty/Kconfig
+++ b/src/mainboard/google/veyron_mighty/Kconfig
@@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_ROCKCHIP_RK3288
select MAINBOARD_DO_NATIVE_VGA_INIT
select MAINBOARD_HAS_CHROMEOS
- select BOARD_ROMSIZE_KB_1024
+ select BOARD_ROMSIZE_KB_4096
select MAINBOARD_HAS_BOOTBLOCK_INIT
select HAVE_HARD_RESET
select RETURN_FROM_VERSTAGE
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 214f0ba..fa382ae 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -95,6 +95,7 @@ config FLASHMAP_OFFSET
hex "Flash Map Offset"
default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
+ default CBFS_SIZE if !ARCH_X86
default 0
help
Offset of flash map in firmware image
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