[coreboot-gerrit] New patch to review for coreboot: 2dc938c rush: Enable dp display
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Apr 13 18:15:27 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9616
-gerrit
commit 2dc938cc6dcc36456bad86ccdb3651658011803c
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date: Tue Jan 6 15:08:54 2015 -0800
rush: Enable dp display
Add dp/sor supporting functions to enable dp panel.
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build rush and ryu
Change-Id: I1cc5a95ef5e3ea7cc701c1cb124a7eb5a5dbd872
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 795a7cddd36bd783cfdd6f1d3f7092bf48ebd8e7
Original-Change-Id: I336336dbbc5a772eec19ba96db8e7b50f6ea1497
Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/238945
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/nvidia/tegra/dc.h | 19 +
src/soc/nvidia/tegra/displayport.h | 2 +
src/soc/nvidia/tegra132/Makefile.inc | 1 +
src/soc/nvidia/tegra132/dp.c | 1635 ++++++++++++++++++++++++-
src/soc/nvidia/tegra132/include/soc/display.h | 8 +
src/soc/nvidia/tegra132/include/soc/sor.h | 930 ++++++++++++++
src/soc/nvidia/tegra132/sor.c | 1100 +++++++++++++++++
7 files changed, 3692 insertions(+), 3 deletions(-)
diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h
index 8808008..0908b15 100644
--- a/src/soc/nvidia/tegra/dc.h
+++ b/src/soc/nvidia/tegra/dc.h
@@ -501,6 +501,25 @@ struct tegra_dc {
void *base;
};
+struct tegra_dc_mode {
+ int pclk;
+ int rated_pclk;
+ int h_ref_to_sync;
+ int v_ref_to_sync;
+ int h_sync_width;
+ int v_sync_width;
+ int h_back_porch;
+ int v_back_porch;
+ int h_active;
+ int v_active;
+ int h_front_porch;
+ int v_front_porch;
+ int stereo_mode;
+ u32 flags;
+ u8 avi_m;
+ u32 vmode;
+};
+
unsigned long READL(void * p);
void WRITEL(unsigned long value, void * p);
diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h
index b7face5..9de0560 100644
--- a/src/soc/nvidia/tegra/displayport.h
+++ b/src/soc/nvidia/tegra/displayport.h
@@ -439,6 +439,8 @@ struct tegra_dc_dp_data {
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204)
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000)
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001)
+#define NV_DPCD_SINK_STATUS (0x00000205)
+#define NV_DPCD_SINK_STATUS_PORT0_IN_SYNC (0x1 << 0)
#define NV_DPCD_LANE0_1_ADJUST_REQ (0x00000206)
#define NV_DPCD_LANE2_3_ADJUST_REQ (0x00000207)
#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 2beeb78..091c186 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -73,6 +73,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi.c
ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi-phy.c
ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c
ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c
+ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c
ramstage-y += soc.c
ramstage-y += spi.c
diff --git a/src/soc/nvidia/tegra132/dp.c b/src/soc/nvidia/tegra132/dp.c
index 7bd35e8..9714d44 100644
--- a/src/soc/nvidia/tegra132/dp.c
+++ b/src/soc/nvidia/tegra132/dp.c
@@ -1,7 +1,7 @@
/*
* drivers/video/tegra/dc/dp.c
*
- * Copyright (c) 2011-2013, NVIDIA Corporation.
+ * Copyright (c) 2011-2015, NVIDIA Corporation.
* Copyright 2014 Google Inc.
*
* This software is licensed under the terms of the GNU General Public
@@ -17,18 +17,1647 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
+#include <device/i2c.h>
+#include <edid.h>
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
#include <soc/display.h>
+#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra/dc.h>
-#include <stdlib.h>
-
+#include <soc/nvidia/tegra/types.h>
+#include <soc/nvidia/tegra/pwm.h>
+#include <soc/nvidia/tegra/displayport.h>
+#include <soc/sor.h>
#include "chip.h"
+#define DO_FAST_LINK_TRAINING 0
+
+struct tegra_dc dc_data;
+
+enum {
+ DP_LT_SUCCESS = 0,
+ DP_LT_FAILED = -1,
+};
+
+struct tegra_dc_dp_data dp_data;
+
+static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
+{
+ void *addr = dp->aux_base + (u32) (reg << 2);
+ u32 reg_val = READL(addr);
+ return reg_val;
+}
+
+static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
+ u32 reg, u32 val)
+{
+ void *addr = dp->aux_base + (u32) (reg << 2);
+ WRITEL(val, addr);
+}
+
+static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
+ u32 reg, u32 mask, u32 exp_val,
+ u32 poll_interval_us,
+ u32 timeout_us)
+{
+ u32 reg_val = 0;
+ u32 temp = timeout_us;
+
+ do {
+ udelay(poll_interval_us);
+ reg_val = tegra_dpaux_readl(dp, reg);
+ if (timeout_us > poll_interval_us)
+ timeout_us -= poll_interval_us;
+ else
+ break;
+ } while ((reg_val & mask) != exp_val);
+
+ if ((reg_val & mask) == exp_val)
+ return 0; /* success */
+ printk(BIOS_ERR,
+ "dpaux_poll_register 0x%x: timeout: "
+ "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
+ reg, reg_val, mask, exp_val);
+ return temp;
+}
+
+static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
+{
+ /* According to DP spec, each aux transaction needs to finish
+ within 40ms. */
+ if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
+ DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
+ DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
+ 100, DP_AUX_TIMEOUT_MS * 1000) != 0) {
+ printk(BIOS_INFO, "dp: DPAUX transaction timeout\n");
+ return -1;
+ }
+ return 0;
+}
+
+static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
+ u32 addr, u8 *data, u32 *size,
+ u32 *aux_stat)
+{
+ int i;
+ u32 reg_val;
+ u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
+ u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
+ u32 temp_data;
+
+ if (*size > DP_AUX_MAX_BYTES)
+ return -1; /* only write one chunk of data */
+
+ /* Make sure the command is write command */
+ switch (cmd) {
+ case DPAUX_DP_AUXCTL_CMD_I2CWR:
+ case DPAUX_DP_AUXCTL_CMD_MOTWR:
+ case DPAUX_DP_AUXCTL_CMD_AUXWR:
+ break;
+ default:
+ printk(BIOS_ERR, "dp: aux write cmd 0x%x is invalid\n", cmd);
+ return -1;
+ }
+
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
+ for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) {
+ memcpy(&temp_data, data, 4);
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data);
+ data += 4;
+ }
+
+ reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
+ reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
+ reg_val |= cmd;
+ reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
+ reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
+
+ while ((timeout_retries > 0) && (defer_retries > 0)) {
+ if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
+ (defer_retries != DP_AUX_DEFER_MAX_TRIES))
+ udelay(1);
+
+ reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
+
+ if (tegra_dpaux_wait_transaction(dp))
+ printk(BIOS_ERR, "dp: aux write transaction timeout\n");
+
+ *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+
+ if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
+ (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
+ (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
+ (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
+ if (timeout_retries-- > 0) {
+ printk(BIOS_INFO, "dp: aux write retry (0x%x)"
+ " -- %d\n",
+ *aux_stat, timeout_retries);
+ /* clear the error bits */
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+ *aux_stat);
+ continue;
+ } else {
+ printk(BIOS_ERR, "dp: aux write got error"
+ " (0x%x)\n", *aux_stat);
+ return -1;
+ }
+ }
+
+ if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
+ (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
+ if (defer_retries-- > 0) {
+ printk(BIOS_INFO, "dp: aux write defer (0x%x)"
+ " -- %d\n", *aux_stat, defer_retries);
+ /* clear the error bits */
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+ *aux_stat);
+ continue;
+ } else {
+ printk(BIOS_ERR, "dp: aux write defer exceeds"
+ " max retries (0x%x)\n", *aux_stat);
+ return -1;
+ }
+ }
+
+ if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
+ DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
+ *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
+ return 0;
+ } else {
+ printk(BIOS_ERR, "dp: aux write failed (0x%x)\n",
+ *aux_stat);
+ return -1;
+ }
+ }
+ /* Should never come to here */
+ return -1;
+}
+
+static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
+ u32 addr, u8 *data, u32 *size,
+ u32 *aux_stat)
+{
+ u32 reg_val;
+ u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
+ u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
+
+ if (*size > DP_AUX_MAX_BYTES)
+ return -1; /* only read one chunk */
+
+ /* Check to make sure the command is read command */
+ switch (cmd) {
+ case DPAUX_DP_AUXCTL_CMD_I2CRD:
+ case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
+ case DPAUX_DP_AUXCTL_CMD_MOTRD:
+ case DPAUX_DP_AUXCTL_CMD_AUXRD:
+ break;
+ default:
+ printk(BIOS_ERR, "dp: aux read cmd 0x%x is invalid\n", cmd);
+ return -1;
+ }
+
+ *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+ if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
+ printk(BIOS_SPEW, "dp: HPD is not detected\n");
+ return -1;
+ }
+
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
+
+ reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
+ reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
+ reg_val |= cmd;
+ reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
+ reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
+ while ((timeout_retries > 0) && (defer_retries > 0)) {
+ if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
+ (defer_retries != DP_AUX_DEFER_MAX_TRIES))
+ udelay(DP_DPCP_RETRY_SLEEP_NS * 2);
+
+ reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
+
+ if (tegra_dpaux_wait_transaction(dp))
+ printk(BIOS_INFO, "dp: aux read transaction timeout\n");
+
+ *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+
+ if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
+ (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
+ (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
+ (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
+ if (timeout_retries-- > 0) {
+ printk(BIOS_INFO, "dp: aux read retry (0x%x)"
+ " -- %d\n", *aux_stat,
+ timeout_retries);
+ /* clear the error bits */
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+ *aux_stat);
+ continue; /* retry */
+ } else {
+ printk(BIOS_ERR, "dp: aux read got error"
+ " (0x%x)\n", *aux_stat);
+ return -1;
+ }
+ }
+
+ if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
+ (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
+ if (defer_retries-- > 0) {
+ printk(BIOS_INFO, "dp: aux read defer (0x%x)"
+ " -- %d\n", *aux_stat, defer_retries);
+ /* clear the error bits */
+ tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+ *aux_stat);
+ continue;
+ } else {
+ printk(BIOS_INFO, "dp: aux read defer exceeds"
+ " max retries (0x%x)\n", *aux_stat);
+ return -1;
+ }
+ }
+
+ if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
+ DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
+ int i;
+ u32 temp_data[4];
+
+ for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i)
+ temp_data[i] = tegra_dpaux_readl(dp,
+ DPAUX_DP_AUXDATA_READ_W(i));
+
+ *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
+ memcpy(data, temp_data, *size);
+
+ return 0;
+ } else {
+ printk(BIOS_ERR, "dp: aux read failed (0x%x\n",
+ *aux_stat);
+ return -1;
+ }
+ }
+ /* Should never come to here */
+ printk(BIOS_ERR, "%s: can't\n", __func__);
+ return -1;
+}
+
+#if DO_FAST_LINK_TRAINING
+static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
+ u8 *data, u32 *size, u32 *aux_stat)
+{
+ u32 finished = 0;
+ u32 cur_size;
+ int ret = 0;
+
+ do {
+ cur_size = *size - finished;
+ if (cur_size > DP_AUX_MAX_BYTES)
+ cur_size = DP_AUX_MAX_BYTES;
+
+ ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
+ data, &cur_size, aux_stat);
+ if (ret)
+ break;
+
+ /* cur_size should be the real size returned */
+ addr += cur_size;
+ data += cur_size;
+ finished += cur_size;
+
+ } while (*size > finished);
+
+ *size = finished;
+ return ret;
+}
+#endif /* DO_FAST_LINK_TRAINING */
+
+static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
+ u8 *data_ptr)
+{
+ u32 size = 1;
+ u32 status = 0;
+ int ret;
+
+ ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
+ cmd, data_ptr, &size, &status);
+ if (ret)
+ printk(BIOS_ERR,
+ "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
+ cmd, status);
+
+ return ret;
+}
+
+static int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
+ u8 data)
+{
+ u32 size = 1;
+ u32 status = 0;
+ int ret;
+
+ ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
+ cmd, &data, &size, &status);
+ if (ret)
+ printk(BIOS_ERR,
+ "dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n",
+ cmd, status);
+ return ret;
+}
+
+static int tegra_dc_i2c_aux_read(struct tegra_dc_dp_data *dp, u32 i2c_addr,
+ u8 addr, u8 *data, u32 *size, u32 *aux_stat)
+{
+ u32 finished = 0;
+ int ret = 0;
+
+ do {
+ u32 cur_size = MIN(DP_AUX_MAX_BYTES, *size - finished);
+
+ u32 len = 1;
+ ret = tegra_dc_dpaux_write_chunk(
+ dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr,
+ &addr, &len, aux_stat);
+ if (ret) {
+ printk(BIOS_ERR, "%s: error sending address to read.\n",
+ __func__);
+ break;
+ }
+
+ ret = tegra_dc_dpaux_read_chunk(
+ dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr,
+ data, &cur_size, aux_stat);
+ if (ret) {
+ printk(BIOS_ERR, "%s: error reading data.\n", __func__);
+ break;
+ }
+
+ /* cur_size should be the real size returned */
+ addr += cur_size;
+ data += cur_size;
+ finished += cur_size;
+ } while (*size > finished);
+
+ *size = finished;
+ return ret;
+}
+
+static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp)
+{
+ /* clear interrupt */
+ tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
+ /* do not enable interrupt for now. Enable them when Isr in place */
+ tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
+
+ tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL,
+ DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 |
+ DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 |
+ 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT |
+ DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE);
+
+ tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE,
+ DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP);
+}
+
+static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
+ const struct tegra_dc_dp_link_config *link_cfg)
+{
+ printk(BIOS_INFO, "DP config: cfg_name "
+ "cfg_value\n");
+ printk(BIOS_INFO, " Lane Count %d\n",
+ link_cfg->max_lane_count);
+ printk(BIOS_INFO, " SupportEnhancedFraming %s\n",
+ link_cfg->support_enhanced_framing ? "Y" : "N");
+ printk(BIOS_INFO, " Bandwidth %d\n",
+ link_cfg->max_link_bw);
+ printk(BIOS_INFO, " bpp %d\n",
+ link_cfg->bits_per_pixel);
+ printk(BIOS_INFO, " EnhancedFraming %s\n",
+ link_cfg->enhanced_framing ? "Y" : "N");
+ printk(BIOS_INFO, " Scramble_enabled %s\n",
+ link_cfg->scramble_ena ? "Y" : "N");
+ printk(BIOS_INFO, " LinkBW %d\n",
+ link_cfg->link_bw);
+ printk(BIOS_INFO, " lane_count %d\n",
+ link_cfg->lane_count);
+ printk(BIOS_INFO, " activespolarity %d\n",
+ link_cfg->activepolarity);
+ printk(BIOS_INFO, " active_count %d\n",
+ link_cfg->active_count);
+ printk(BIOS_INFO, " tu_size %d\n",
+ link_cfg->tu_size);
+ printk(BIOS_INFO, " active_frac %d\n",
+ link_cfg->active_frac);
+ printk(BIOS_INFO, " watermark %d\n",
+ link_cfg->watermark);
+ printk(BIOS_INFO, " hblank_sym %d\n",
+ link_cfg->hblank_sym);
+ printk(BIOS_INFO, " vblank_sym %d\n",
+ link_cfg->vblank_sym);
+}
+
+static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
+ struct tegra_dc_dp_link_config *link_cfg)
+{
+
+ switch (link_cfg->link_bw) {
+ case SOR_LINK_SPEED_G1_62:
+ if (link_cfg->max_link_bw > SOR_LINK_SPEED_G1_62)
+ link_cfg->link_bw = SOR_LINK_SPEED_G2_7;
+ link_cfg->lane_count /= 2;
+ break;
+ case SOR_LINK_SPEED_G2_7:
+ link_cfg->link_bw = SOR_LINK_SPEED_G1_62;
+ break;
+ case SOR_LINK_SPEED_G5_4:
+ if (link_cfg->lane_count == 1) {
+ link_cfg->link_bw = SOR_LINK_SPEED_G2_7;
+ link_cfg->lane_count = link_cfg->max_lane_count;
+ } else
+ link_cfg->lane_count /= 2;
+ break;
+ default:
+ printk(BIOS_ERR, "dp: Error link rate %d\n", link_cfg->link_bw);
+ return DP_LT_FAILED;
+ }
+
+ return (link_cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED;
+}
+
+/* Calcuate if given cfg can meet the mode request. */
+/* Return true if mode is possible, false otherwise. */
+static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
+ const struct soc_nvidia_tegra132_config *config,
+ struct tegra_dc_dp_link_config *link_cfg)
+{
+ const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000;
+ const u64 f = 100000; /* precision factor */
+
+ u32 num_linkclk_line; /* Number of link clocks per line */
+ u64 ratio_f; /* Ratio of incoming to outgoing data rate */
+
+ u64 frac_f;
+ u64 activesym_f; /* Activesym per TU */
+ u64 activecount_f;
+ u32 activecount;
+ u32 activepolarity;
+ u64 approx_value_f;
+ u32 activefrac = 0;
+ u64 accumulated_error_f = 0;
+ u32 lowest_neg_activecount = 0;
+ u32 lowest_neg_activepolarity = 0;
+ u32 lowest_neg_tusize = 64;
+ u32 num_symbols_per_line;
+ u64 lowest_neg_activefrac = 0;
+ u64 lowest_neg_error_f = 64 * f;
+ u64 watermark_f;
+
+ int i;
+ int neg;
+
+ printk(BIOS_INFO, "dp: %s\n", __func__);
+
+ if (!link_rate || !link_cfg->lane_count || !config->pixel_clock ||
+ !link_cfg->bits_per_pixel)
+ return -1;
+
+ if ((u64)config->pixel_clock * link_cfg->bits_per_pixel >=
+ (u64)link_rate * 8 * link_cfg->lane_count)
+ return -1;
+
+ num_linkclk_line = (u32)((u64)link_rate * (u64)config->xres /
+ config->pixel_clock);
+
+ ratio_f = (u64)config->pixel_clock * link_cfg->bits_per_pixel * f;
+ ratio_f /= 8;
+ ratio_f = (u64)(ratio_f / (link_rate * link_cfg->lane_count));
+
+ for (i = 64; i >= 32; --i) {
+ activesym_f = ratio_f * i;
+ activecount_f = (u64)(activesym_f / (u32)f) * f;
+ frac_f = activesym_f - activecount_f;
+ activecount = (u32)((u64)(activecount_f / (u32)f));
+
+ if (frac_f < (f / 2)) /* fraction < 0.5 */
+ activepolarity = 0;
+ else {
+ activepolarity = 1;
+ frac_f = f - frac_f;
+ }
+
+ if (frac_f != 0) {
+ frac_f = (u64)((f * f) / frac_f); /* 1/fraction */
+ if (frac_f > (15 * f))
+ activefrac = activepolarity ? 1 : 15;
+ else
+ activefrac = activepolarity ?
+ (u32)((u64)(frac_f / (u32)f)) + 1 :
+ (u32)((u64)(frac_f / (u32)f));
+ }
+
+ if (activefrac == 1)
+ activepolarity = 0;
+
+ if (activepolarity == 1)
+ approx_value_f = activefrac ? (u64)(
+ (activecount_f + (activefrac * f - f) * f) /
+ (activefrac * f)) :
+ activecount_f + f;
+ else
+ approx_value_f = activefrac ?
+ activecount_f + (u64)(f / activefrac) :
+ activecount_f;
+
+ if (activesym_f < approx_value_f) {
+ accumulated_error_f = num_linkclk_line *
+ (u64)((approx_value_f - activesym_f) / i);
+ neg = 1;
+ } else {
+ accumulated_error_f = num_linkclk_line *
+ (u64)((activesym_f - approx_value_f) / i);
+ neg = 0;
+ }
+
+ if ((neg && (lowest_neg_error_f > accumulated_error_f)) ||
+ (accumulated_error_f == 0)) {
+ lowest_neg_error_f = accumulated_error_f;
+ lowest_neg_tusize = i;
+ lowest_neg_activecount = activecount;
+ lowest_neg_activepolarity = activepolarity;
+ lowest_neg_activefrac = activefrac;
+
+ if (accumulated_error_f == 0)
+ break;
+ }
+ }
+
+ if (lowest_neg_activefrac == 0) {
+ link_cfg->activepolarity = 0;
+ link_cfg->active_count = lowest_neg_activepolarity ?
+ lowest_neg_activecount : lowest_neg_activecount - 1;
+ link_cfg->tu_size = lowest_neg_tusize;
+ link_cfg->active_frac = 1;
+ } else {
+ link_cfg->activepolarity = lowest_neg_activepolarity;
+ link_cfg->active_count = (u32)lowest_neg_activecount;
+ link_cfg->tu_size = lowest_neg_tusize;
+ link_cfg->active_frac = (u32)lowest_neg_activefrac;
+ }
+
+ watermark_f = (u64)((ratio_f * link_cfg->tu_size * (f - ratio_f)) / f);
+ link_cfg->watermark = (u32)((u64)((watermark_f + lowest_neg_error_f) /
+ f)) + link_cfg->bits_per_pixel / 4 - 1;
+ num_symbols_per_line = (config->xres * link_cfg->bits_per_pixel) /
+ (8 * link_cfg->lane_count);
+
+ if (link_cfg->watermark > 30) {
+ printk(BIOS_INFO,
+ "dp: sor setting: unable to get a good tusize, "
+ "force watermark to 30.\n");
+ link_cfg->watermark = 30;
+ return -1;
+ } else if (link_cfg->watermark > num_symbols_per_line) {
+ printk(BIOS_INFO,
+ "dp: sor setting: force watermark to the number "
+ "of symbols in the line.\n");
+ link_cfg->watermark = num_symbols_per_line;
+ return -1;
+ }
+
+ /* Refer to dev_disp.ref for more information. */
+ /* # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
+ /* SetRasterBlankStart.X - 7) * link_clk / pclk) */
+ /* - 3 * enhanced_framing - Y */
+ /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */
+ link_cfg->hblank_sym = (int)((u64)(((u64)(config->hback_porch +
+ config->hfront_porch + config->hsync_width - 7) *
+ link_rate) / config->pixel_clock)) -
+ 3 * link_cfg->enhanced_framing -
+ (12 / link_cfg->lane_count);
+
+ if (link_cfg->hblank_sym < 0)
+ link_cfg->hblank_sym = 0;
+
+
+ /* Refer to dev_disp.ref for more information. */
+ /* # symbols/vblank = ((SetRasterBlankStart.X - */
+ /* SetRasterBlankEen.X - 25) * link_clk / pclk) */
+ /* - Y - 1; */
+ /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */
+ link_cfg->vblank_sym = (int)((u64)((u64)(config->xres - 25)
+ * link_rate / config->pixel_clock)) - (36 /
+ link_cfg->lane_count) - 4;
+
+ if (link_cfg->vblank_sym < 0)
+ link_cfg->vblank_sym = 0;
+
+ link_cfg->is_valid = 1;
+ tegra_dc_dp_dump_link_cfg(dp, link_cfg);
+
+ return 0;
+}
+
+static int tegra_dc_dp_init_max_link_cfg(
+ struct soc_nvidia_tegra132_config *config,
+ struct tegra_dc_dp_data *dp,
+ struct tegra_dc_dp_link_config *link_cfg)
+{
+ u8 dpcd_data;
+ int ret;
+
+ printk(BIOS_INFO, "dp: %s\n", __func__);
+
+ CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
+ &dpcd_data));
+ link_cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
+ link_cfg->tps3_supported = (dpcd_data &
+ NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ? 1 : 0;
+
+ link_cfg->support_enhanced_framing =
+ (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
+ 1 : 0;
+
+ CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
+ &dpcd_data));
+ link_cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT)
+ ? 1 : 0;
+
+ CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL,
+ &link_cfg->aux_rd_interval));
+
+ CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
+ &link_cfg->max_link_bw));
+
+ link_cfg->bits_per_pixel = config->panel_bits_per_pixel;
+
+ /*
+ * Set to a high value for link training and attach.
+ * Will be re-programmed when dp is enabled.
+ */
+ link_cfg->drive_current = config->dp.drive_current;
+ link_cfg->preemphasis = config->dp.preemphasis;
+ link_cfg->postcursor = config->dp.postcursor;
+
+ CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
+ &dpcd_data));
+ link_cfg->alt_scramber_reset_cap =
+ (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
+ 1 : 0;
+ link_cfg->only_enhanced_framing =
+ (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
+ 1 : 0;
+
+ link_cfg->lane_count = link_cfg->max_lane_count;
+ link_cfg->link_bw = link_cfg->max_link_bw;
+ link_cfg->enhanced_framing = link_cfg->support_enhanced_framing;
+
+ tegra_dc_dp_calc_config(dp, config, link_cfg);
+ return 0;
+}
+
+static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, int ena)
+{
+ int ret;
+
+ u8 dpcd_data = ena ?
+ NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE :
+ NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE;
+
+ CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_EDP_CONFIG_SET,
+ dpcd_data));
+
+ /* Also reset the scrambler to 0xfffe */
+ tegra_dc_sor_set_internal_panel(&dp->sor, ena);
+ return 0;
+}
+
+static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data *dp, u8 link_bw)
+{
+ tegra_dc_sor_set_link_bandwidth(&dp->sor, link_bw);
+
+ /* Sink side */
+ return tegra_dc_dp_dpcd_write(dp, NV_DPCD_LINK_BANDWIDTH_SET, link_bw);
+}
+
+static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp,
+ const struct tegra_dc_dp_link_config *link_cfg)
+{
+ u8 dpcd_data;
+ int ret;
+
+ /* check if panel support enhanched_framing */
+ dpcd_data = link_cfg->lane_count;
+ if (link_cfg->enhanced_framing)
+ dpcd_data |= NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T;
+ CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_LANE_COUNT_SET,
+ dpcd_data));
+
+ tegra_dc_sor_set_lane_count(&dp->sor, link_cfg->lane_count);
+
+ /* Also power down lanes that will not be used */
+ return 0;
+}
+
+#if DO_FAST_LINK_TRAINING
+static int tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp,
+ const struct tegra_dc_dp_link_config *link_cfg)
+{
+ u32 lane;
+ u8 mask;
+ u8 data;
+ int ret;
+
+ for (lane = 0; lane < link_cfg->lane_count; ++lane) {
+ CHECK_RET(tegra_dc_dp_dpcd_read(dp, (lane/2) ?
+ NV_DPCD_LANE2_3_STATUS : NV_DPCD_LANE0_1_STATUS,
+ &data));
+ mask = (lane & 1) ?
+ NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES |
+ NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES |
+ NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES :
+ NV_DPCD_STATUS_LANEX_CR_DONE_YES |
+ NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES |
+ NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES;
+ if ((data & mask) != mask)
+ return -1;
+ }
+ return 0;
+}
+#endif /* DO_FAST_LINK_TRAINING */
+
+static int tegra_dp_channel_eq_status(struct tegra_dc_dp_data *dp)
+{
+ u32 cnt;
+ u32 n_lanes = dp->link_cfg.lane_count;
+ u8 data;
+ u8 ce_done = 1;
+
+ for (cnt = 0; cnt < n_lanes / 2; cnt++) {
+ tegra_dc_dp_dpcd_read(dp, (NV_DPCD_LANE0_1_STATUS + cnt),
+ &data);
+
+ if (n_lanes == 1) {
+ ce_done =
+ (data & (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) &&
+ (data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT));
+ break;
+ } else
+ if (!(data & (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) ||
+ !(data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) ||
+ !(data & (0x1 << NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT)) ||
+ !(data & (0x1 << NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT)))
+ return 0;
+ }
+
+ if (ce_done) {
+ tegra_dc_dp_dpcd_read(dp, NV_DPCD_LANE_ALIGN_STATUS_UPDATED,
+ &data);
+ if (!(data & NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES))
+ ce_done = 0;
+ }
+
+ return ce_done;
+}
+
+static u8 tegra_dp_clock_recovery_status(struct tegra_dc_dp_data *dp)
+{
+ u32 cnt;
+ u32 n_lanes = dp->link_cfg.lane_count;
+ u8 data_ptr;
+
+ for (cnt = 0; cnt < n_lanes / 2; cnt++) {
+ tegra_dc_dp_dpcd_read(dp,
+ (NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr);
+
+ if (n_lanes == 1)
+ return (data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ? 1 : 0;
+ else if (!(data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ||
+ !(data_ptr & (NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES)))
+ return 0;
+ }
+
+ return 1;
+}
+
+static void tegra_dp_lt_adjust(struct tegra_dc_dp_data *dp,
+ u32 pe[4], u32 vs[4], u32 pc[4],
+ u8 pc_supported)
+{
+ size_t cnt;
+ u8 data_ptr;
+ u32 n_lanes = dp->link_cfg.lane_count;
+
+ for (cnt = 0; cnt < n_lanes / 2; cnt++) {
+ tegra_dc_dp_dpcd_read(dp,
+ (NV_DPCD_LANE0_1_ADJUST_REQ + cnt), &data_ptr);
+ pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >>
+ NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT;
+ vs[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >>
+ NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT;
+ pe[1 + 2 * cnt] =
+ (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK) >>
+ NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT;
+ vs[1 + 2 * cnt] =
+ (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK) >>
+ NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT;
+ }
+ if (pc_supported) {
+ tegra_dc_dp_dpcd_read(dp,
+ NV_DPCD_ADJUST_REQ_POST_CURSOR2, &data_ptr);
+ for (cnt = 0; cnt < n_lanes; cnt++) {
+ pc[cnt] = (data_ptr >>
+ NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(cnt)) &
+ NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK;
+ }
+ }
+}
+
+static inline u32 tegra_dp_wait_aux_training(struct tegra_dc_dp_data *dp,
+ u8 is_clk_recovery)
+{
+ if (!dp->link_cfg.aux_rd_interval)
+ is_clk_recovery ? udelay(200) :
+ udelay(500);
+ else
+ mdelay(dp->link_cfg.aux_rd_interval * 4);
+
+ return dp->link_cfg.aux_rd_interval;
+}
+
+static void tegra_dp_tpg(struct tegra_dc_dp_data *dp, u32 tp, u32 n_lanes)
+{
+ u8 data = (tp == training_pattern_disabled)
+ ? (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F)
+ : (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T);
+
+ tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, tp, &dp->link_cfg);
+ tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, data);
+}
+
+static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
+ const struct tegra_dc_dp_link_config *link_cfg)
+{
+ u8 dpcd_data;
+ u32 retry;
+
+ if (link_cfg->lane_count == 0) {
+ printk(BIOS_ERR, "dp: error: lane count is 0. "
+ "Can not set link config.\n");
+ return DP_LT_FAILED;
+ }
+
+ /* Set power state if it is not in normal level */
+ if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data))
+ return DP_LT_FAILED;
+
+ if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) {
+ dpcd_data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
+
+ /* DP spec requires 3 retries */
+ for (retry = 3; retry > 0; --retry) {
+ if (tegra_dc_dp_dpcd_write(dp, NV_DPCD_SET_POWER,
+ dpcd_data))
+ break;
+ if (retry == 1) {
+ printk(BIOS_ERR, "dp: Failed to set DP panel"
+ " power\n");
+ return DP_LT_FAILED;
+ }
+ }
+ }
+
+ /* Enable ASSR if possible */
+ if (link_cfg->alt_scramber_reset_cap)
+ if (tegra_dc_dp_set_assr(dp, 1))
+ return DP_LT_FAILED;
+
+ if (tegra_dp_set_link_bandwidth(dp, link_cfg->link_bw)) {
+ printk(BIOS_ERR, "dp: Failed to set link bandwidth\n");
+ return DP_LT_FAILED;
+ }
+ if (tegra_dp_set_lane_count(dp, link_cfg)) {
+ printk(BIOS_ERR, "dp: Failed to set lane count\n");
+ return DP_LT_FAILED;
+ }
+ tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, training_pattern_none,
+ link_cfg);
+ return DP_LT_SUCCESS;
+}
+
+static int tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
+ struct tegra_dc_dp_link_config *cfg)
+{
+ struct tegra_dc_dp_link_config tmp_cfg;
+
+ tmp_cfg = dp->link_cfg;
+ cfg->is_valid = 0;
+
+ if (_tegra_dp_lower_link_config(dp, cfg))
+ goto fail;
+
+ if (tegra_dc_dp_calc_config(dp, dp->dc->config, cfg))
+ goto fail;
+ tegra_dp_link_config(dp, cfg);
+
+ return DP_LT_SUCCESS;
+fail:
+ dp->link_cfg = tmp_cfg;
+ tegra_dp_link_config(dp, &tmp_cfg);
+ return DP_LT_FAILED;
+}
+
+static void tegra_dp_lt_config(struct tegra_dc_dp_data *dp,
+ u32 pe[4], u32 vs[4], u32 pc[4])
+{
+ struct tegra_dc_sor_data *sor = &dp->sor;
+ u32 n_lanes = dp->link_cfg.lane_count;
+ u8 pc_supported = dp->link_cfg.tps3_supported;
+ u32 cnt;
+ u32 val;
+
+ for (cnt = 0; cnt < n_lanes; cnt++) {
+ u32 mask = 0;
+ u32 pe_reg, vs_reg, pc_reg;
+ u32 shift = 0;
+
+ switch (cnt) {
+ case 0:
+ mask = NV_SOR_PR_LANE2_DP_LANE0_MASK;
+ shift = NV_SOR_PR_LANE2_DP_LANE0_SHIFT;
+ break;
+ case 1:
+ mask = NV_SOR_PR_LANE1_DP_LANE1_MASK;
+ shift = NV_SOR_PR_LANE1_DP_LANE1_SHIFT;
+ break;
+ case 2:
+ mask = NV_SOR_PR_LANE0_DP_LANE2_MASK;
+ shift = NV_SOR_PR_LANE0_DP_LANE2_SHIFT;
+ break;
+ case 3:
+ mask = NV_SOR_PR_LANE3_DP_LANE3_MASK;
+ shift = NV_SOR_PR_LANE3_DP_LANE3_SHIFT;
+ break;
+ default:
+ printk(BIOS_ERR,
+ "dp: incorrect lane cnt\n");
+ }
+
+ pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]];
+ vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]];
+ pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]];
+
+ tegra_dp_set_pe_vs_pc(sor, mask, pe_reg << shift,
+ vs_reg << shift, pc_reg << shift, pc_supported);
+ }
+
+ tegra_dp_disable_tx_pu(&dp->sor);
+ udelay(20);
+
+ for (cnt = 0; cnt < n_lanes; cnt++) {
+ u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]);
+ u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]);
+
+ val = (vs[cnt] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT) |
+ (max_vs_flag ?
+ NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T :
+ NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F) |
+ (pe[cnt] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT) |
+ (max_pe_flag ?
+ NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T :
+ NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F);
+ tegra_dc_dp_dpcd_write(dp,
+ (NV_DPCD_TRAINING_LANE0_SET + cnt), val);
+ }
+
+ if (pc_supported) {
+ for (cnt = 0; cnt < n_lanes / 2; cnt++) {
+ u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]);
+ u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]);
+ val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) |
+ (max_pc_flag0 ?
+ NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T :
+ NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F) |
+ (pc[cnt + 1] <<
+ NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT) |
+ (max_pc_flag1 ?
+ NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T :
+ NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F);
+ tegra_dc_dp_dpcd_write(dp,
+ (NV_DPCD_TRAINING_LANE0_1_SET2 + cnt), val);
+ }
+ }
+}
+
+static int _tegra_dp_channel_eq(struct tegra_dc_dp_data *dp, u32 pe[4],
+ u32 vs[4], u32 pc[4], u8 pc_supported,
+ u32 n_lanes)
+{
+ u32 retry_cnt;
+
+ for (retry_cnt = 0; retry_cnt < 4; retry_cnt++) {
+ if (retry_cnt) {
+ tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported);
+ tegra_dp_lt_config(dp, pe, vs, pc);
+ }
+
+ tegra_dp_wait_aux_training(dp, 0);
+
+ if (!tegra_dp_clock_recovery_status(dp)) {
+ printk(BIOS_ERR, "dp: CR failed in channel EQ"
+ " sequence!\n");
+ break;
+ }
+
+ if (tegra_dp_channel_eq_status(dp))
+ return DP_LT_SUCCESS;
+ }
+
+ return DP_LT_FAILED;
+}
+
+static int tegra_dp_channel_eq(struct tegra_dc_dp_data *dp,
+ u32 pe[4], u32 vs[4], u32 pc[4])
+{
+ u32 n_lanes = dp->link_cfg.lane_count;
+ u8 pc_supported = dp->link_cfg.tps3_supported;
+ int err;
+ u32 tp_src = training_pattern_2;
+
+ if (pc_supported)
+ tp_src = training_pattern_3;
+
+ tegra_dp_tpg(dp, tp_src, n_lanes);
+
+ err = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes);
+
+ tegra_dp_tpg(dp, training_pattern_disabled, n_lanes);
+
+ return err;
+}
+
+static int _tegra_dp_clk_recovery(struct tegra_dc_dp_data *dp, u32 pe[4],
+ u32 vs[4], u32 pc[4], u8 pc_supported,
+ u32 n_lanes)
+{
+ u32 vs_temp[4];
+ u32 retry_cnt = 0;
+
+ do {
+ tegra_dp_lt_config(dp, pe, vs, pc);
+ tegra_dp_wait_aux_training(dp, 1);
+
+ if (tegra_dp_clock_recovery_status(dp))
+ return DP_LT_SUCCESS;
+
+ memcpy(vs_temp, vs, sizeof(vs_temp));
+ tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported);
+
+ if (memcmp(vs_temp, vs, sizeof(vs_temp)))
+ retry_cnt = 0;
+ else
+ ++retry_cnt;
+ } while (retry_cnt < 5);
+
+ return DP_LT_FAILED;
+}
+
+static int tegra_dp_clk_recovery(struct tegra_dc_dp_data *dp,
+ u32 pe[4], u32 vs[4], u32 pc[4])
+{
+ u32 n_lanes = dp->link_cfg.lane_count;
+ u8 pc_supported = dp->link_cfg.tps3_supported;
+ int err;
+
+ tegra_dp_tpg(dp, training_pattern_1, n_lanes);
+
+ err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes);
+ if (err < 0)
+ tegra_dp_tpg(dp, training_pattern_disabled, n_lanes);
+
+ return err;
+}
+
+static int tegra_dc_dp_full_link_training(struct tegra_dc_dp_data *dp)
+{
+ struct tegra_dc_sor_data *sor = &dp->sor;
+ int err;
+ u32 pe[4], vs[4], pc[4];
+
+ printk(BIOS_INFO, "dp: %s\n", __func__);
+ tegra_sor_precharge_lanes(sor);
+
+retry_cr:
+ memset(pe, preEmphasis_Disabled, sizeof(pe));
+ memset(vs, driveCurrent_Level0, sizeof(vs));
+ memset(pc, postCursor2_Level0, sizeof(pc));
+
+ err = tegra_dp_clk_recovery(dp, pe, vs, pc);
+ if (err != DP_LT_SUCCESS) {
+ if (!tegra_dp_lower_link_config(dp, &dp->link_cfg))
+ goto retry_cr;
+
+ printk(BIOS_ERR, "dp: clk recovery failed\n");
+ goto fail;
+ }
+
+ err = tegra_dp_channel_eq(dp, pe, vs, pc);
+ if (err != DP_LT_SUCCESS) {
+ if (!tegra_dp_lower_link_config(dp, &dp->link_cfg))
+ goto retry_cr;
+
+ printk(BIOS_ERR,
+ "dp: channel equalization failed\n");
+ goto fail;
+ }
+
+ tegra_dc_dp_dump_link_cfg(dp, &dp->link_cfg);
+
+ return 0;
+
+fail:
+ return err;
+}
+
+/*
+ * All link training functions are ported from kernel dc driver.
+ * See more details at drivers/video/tegra/dc/dp.c
+ */
+#if DO_FAST_LINK_TRAINING
+static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp,
+ const struct tegra_dc_dp_link_config *link_cfg)
+{
+ struct tegra_dc_sor_data *sor = &dp->sor;
+ u8 link_bw;
+ u8 lane_count;
+ u16 data16;
+ u32 data32;
+ u32 size;
+ u32 status;
+ int j;
+ u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4);
+
+
+ printk(BIOS_INFO, "dp: %s\n", __func__);
+
+ tegra_dc_sor_set_lane_parm(sor, link_cfg);
+ tegra_dc_dp_dpcd_write(dp, NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET,
+ NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B);
+
+ /* Send TP1 */
+ tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg);
+ tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
+ NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1);
+
+ for (j = 0; j < link_cfg->lane_count; ++j)
+ tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_LANE0_SET + j,
+ 0x24);
+ udelay(520);
+
+ size = sizeof(data16);
+ tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
+ NV_DPCD_LANE0_1_STATUS, (u8 *)&data16, &size, &status);
+ status = mask & 0x1111;
+ if ((data16 & status) != status) {
+ printk(BIOS_ERR,
+ "dp: Link training error for TP1 (%#x)\n", data16);
+ return -EFAULT;
+ }
+
+ /* enable ASSR */
+ tegra_dc_dp_set_assr(dp, link_cfg->scramble_ena);
+ tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg);
+
+ tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
+ link_cfg->link_bw == 20 ? 0x23 : 0x22);
+ for (j = 0; j < link_cfg->lane_count; ++j)
+ tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_LANE0_SET + j,
+ 0x24);
+ udelay(520);
+
+ size = sizeof(data32);
+ tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
+ NV_DPCD_LANE0_1_STATUS, (u8 *)&data32, &size, &status);
+ if ((data32 & mask) != (0x7777 & mask)) {
+ printk(BIOS_ERR,
+ "dp: Link training error for TP2/3 (0x%x)\n", data32);
+ return -EFAULT;
+ }
+
+ tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled,
+ link_cfg);
+ tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, 0);
+
+ if (tegra_dc_dp_link_trained(dp, link_cfg)) {
+ tegra_dc_sor_read_link_config(&dp->sor, &link_bw,
+ &lane_count);
+ printk(BIOS_ERR,
+ "Fast link trainging failed, link bw %d, lane # %d\n",
+ link_bw, lane_count);
+ return -EFAULT;
+ }
+
+ printk(BIOS_INFO,
+ "Fast link trainging succeeded, link bw %d, lane %d\n",
+ link_cfg->link_bw, link_cfg->lane_count);
+
+ return 0;
+}
+#endif /* DO_FAST_LINK_TRAINING */
+
+static int tegra_dp_do_link_training(struct tegra_dc_dp_data *dp,
+ const struct tegra_dc_dp_link_config *link_cfg)
+{
+ u8 link_bw;
+ u8 lane_count;
+#if DO_FAST_LINK_TRAINING
+ int ret;
+
+ /* Now do the fast link training for eDP */
+ ret = tegra_dc_dp_fast_link_training(dp, link_cfg);
+ if (ret) {
+ printk(BIOS_ERR, "dp: fast link training failed\n");
+
+ /* Try full link training then */
+ if (tegra_dc_dp_full_link_training(dp)) {
+ printk(BIOS_ERR, "dp: full link training failed\n");
+ return ret;
+ }
+ } else {
+ /* set to a known-good drive setting if fast link succeeded */
+ tegra_dc_sor_set_voltage_swing(&dp->sor);
+ }
+#else
+ if (tegra_dc_dp_full_link_training(dp)) {
+ printk(BIOS_ERR, "dp: full link training failed\n");
+ return -EFAULT;
+ }
+#endif
+
+ /* Everything goes well, double check the link config */
+ /* TODO: record edc/c2 data for debugging */
+ tegra_dc_sor_read_link_config(&dp->sor, &link_bw, &lane_count);
+
+ if ((link_cfg->link_bw == link_bw) &&
+ (link_cfg->lane_count == lane_count))
+ return 0;
+ else
+ return -EFAULT;
+}
+
+static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp,
+ struct tegra_dc_dp_link_config *link_cfg,
+ const struct soc_nvidia_tegra132_config *config)
+{
+ struct tegra_dc_dp_link_config temp_cfg;
+
+ if (!config->pixel_clock || !config->xres || !config->yres) {
+ printk(BIOS_ERR,
+ "dp: error mode configuration");
+ return -EINVAL;
+ }
+ if (!link_cfg->max_link_bw || !link_cfg->max_lane_count) {
+ printk(BIOS_ERR,
+ "dp: error link configuration");
+ return -EINVAL;
+ }
+
+ link_cfg->is_valid = 0;
+
+ memcpy(&temp_cfg, link_cfg, sizeof(temp_cfg));
+
+ temp_cfg.link_bw = temp_cfg.max_link_bw;
+ temp_cfg.lane_count = temp_cfg.max_lane_count;
+
+ /*
+ * set to max link config
+ */
+ if ((!tegra_dc_dp_calc_config(dp, config, &temp_cfg)) &&
+ (!tegra_dp_link_config(dp, &temp_cfg)) &&
+ (!tegra_dp_do_link_training(dp, &temp_cfg)))
+ /* the max link cfg is doable */
+ memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg));
+
+ return link_cfg->is_valid ? 0 : -EFAULT;
+}
+
+static void tegra_dp_update_config(struct tegra_dc_dp_data *dp,
+ struct soc_nvidia_tegra132_config *config)
+{
+ struct edid edid;
+ u8 buf[128] = {0};
+ u32 size = sizeof(buf), aux_stat = 0;
+
+ printk(BIOS_ERR, "%s: enable r/w dump.\n",
+ __func__);
+
+ tegra_dc_dpaux_enable(dp);
+ if (tegra_dc_i2c_aux_read(dp, TEGRA_EDID_I2C_ADDRESS, 0, buf, &size,
+ &aux_stat)) {
+ printk(BIOS_ERR, "%s: Failed to read EDID. Use defaults.\n",
+ __func__);
+ return;
+ }
+
+ if (decode_edid(buf, sizeof(buf), &edid)) {
+ printk(BIOS_ERR, "%s: Failed to decode EDID. Use defaults.\n",
+ __func__);
+ return;
+ }
+
+ config->xres = config->display_xres = edid.ha;
+ config->yres = config->display_yres = edid.va;
+
+ config->pixel_clock = edid.pixel_clock * 1000;
+
+ config->hfront_porch = edid.hso;
+ config->hsync_width = edid.hspw;
+ config->hback_porch = edid.hbl - edid.hso - edid.hspw;
+
+ config->vfront_porch = edid.vso;
+ config->vsync_width = edid.vspw;
+ config->vback_porch = edid.vbl - edid.vso - edid.vspw;
+
+ /**
+ * Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32,
+ * so we should keep the default value in device config.
+ *
+ * EDID v1.3 panels may not have color depth info, so we need to check
+ * if these values are zero before updating config.
+ */
+ if (edid.panel_bits_per_pixel)
+ config->panel_bits_per_pixel = edid.panel_bits_per_pixel;
+ if (edid.panel_bits_per_color)
+ config->color_depth = edid.panel_bits_per_color;
+ printk(BIOS_SPEW, "%s: configuration updated by EDID.\n", __func__);
+}
+
+void dp_init(void *_config)
+{
+ struct soc_nvidia_tegra132_config *config = (void *)_config;
+ struct tegra_dc *dc = config->dc_data;
+ struct tegra_dc_dp_data *dp = &dp_data;
+
+ /* set up links among config, dc, dp and sor */
+ dp->dc = dc;
+ dc->out = dp;
+ dp->sor.dc = dc;
+
+ dp->sor.power_is_up = 0;
+ dp->sor.base = (void *)TEGRA_ARM_SOR;
+ dp->sor.pmc_base = (void *)TEGRA_PMC_BASE;
+ dp->sor.portnum = 0;
+ dp->sor.link_cfg = &dp->link_cfg;
+ dp->aux_base = (void *)TEGRA_ARM_DPAUX;
+ dp->link_cfg.is_valid = 0;
+ dp->enabled = 0;
+
+ tegra_dp_update_config(dp, config);
+}
+
+static void tegra_dp_hpd_config(struct tegra_dc_dp_data *dp,
+ struct soc_nvidia_tegra132_config *config)
+{
+ u32 val;
+
+ val = config->dp.hpd_plug_min_us |
+ (config->dp.hpd_unplug_min_us <<
+ DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT);
+ tegra_dpaux_writel(dp, DPAUX_HPD_CONFIG, val);
+
+ tegra_dpaux_writel(dp, DPAUX_HPD_IRQ_CONFIG, config->dp.hpd_irq_min_us);
+}
+
+static int tegra_dp_hpd_plug(struct tegra_dc_dp_data *dp, int timeout_ms)
+{
+ u32 val;
+ u32 timeout = timeout_ms * 1000;
+ do {
+ val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+ if (val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)
+ return 0;
+ udelay(100);
+ timeout -= 100;
+ } while (timeout > 0);
+ return -1;
+}
+
+static int tegra_dc_dp_sink_out_of_sync(struct tegra_dc_dp_data *dp,
+ u32 delay_ms)
+{
+ u8 dpcd_data;
+ int out_of_sync;
+
+ mdelay(delay_ms);
+ tegra_dc_dp_dpcd_read(dp, NV_DPCD_SINK_STATUS, &dpcd_data);
+
+ out_of_sync = ((dpcd_data & NV_DPCD_SINK_STATUS_PORT0_IN_SYNC) !=
+ NV_DPCD_SINK_STATUS_PORT0_IN_SYNC);
+
+ if (out_of_sync)
+ printk(BIOS_ERR,
+ "SINK receive port 0 is out of synchronization\n");
+ else
+ printk(BIOS_INFO,
+ "SINK is in synchronization\n");
+
+ return out_of_sync;
+}
+
+static void tegra_dc_dp_check_sink(struct tegra_dc_dp_data *dp,
+ struct soc_nvidia_tegra132_config *config)
+{
+
+ u8 max_retry = 3;
+ int delay_frame;
+
+ /* DP TCON may skip some main stream frames, thus we need to wait
+ some delay before reading the DPCD SINK STATUS register, starting
+ from 5 */
+ delay_frame = 5;
+
+ while (tegra_dc_dp_sink_out_of_sync(dp, FRAME_IN_MS * delay_frame) &&
+ max_retry--) {
+ tegra_dc_detach(&dp->sor);
+ if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, config)) {
+ printk(BIOS_ERR, "dp: %s: error to configure link\n",
+ __func__);
+ continue;
+ }
+
+ tegra_dc_sor_set_power_state(&dp->sor, 1);
+ tegra_dc_sor_attach(&dp->sor);
+
+ /* Increase delay_frame for next try in case the sink is
+ skipping more frames */
+ delay_frame += 10;
+ }
+}
+
+void dp_enable(void *_dp)
+{
+ struct tegra_dc_dp_data *dp = _dp;
+ struct tegra_dc *dc = dp->dc;
+ struct soc_nvidia_tegra132_config *config = dc->config;
+
+ u8 data;
+ u32 retry;
+ int ret;
+
+ tegra_dc_dpaux_enable(dp);
+
+ tegra_dp_hpd_config(dp, config);
+ if (tegra_dp_hpd_plug(dp, config->dp.vdd_to_hpd_delay_ms) < 0) {
+ printk(BIOS_ERR, "dp: hpd plug failed\n");
+ goto error_enable;
+ }
+
+ if (tegra_dc_dp_init_max_link_cfg(config, dp, &dp->link_cfg)) {
+ printk(BIOS_ERR, "dp: failed to init link configuration\n");
+ goto error_enable;
+ }
+
+ tegra_dc_sor_enable_dp(&dp->sor);
+
+ tegra_dc_sor_set_panel_power(&dp->sor, 1);
+
+ /* Write power on to DPCD */
+ data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
+ retry = 0;
+ do {
+ ret = tegra_dc_dp_dpcd_write(dp,
+ NV_DPCD_SET_POWER, data);
+ } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret);
+
+ if (ret || retry >= DP_POWER_ON_MAX_TRIES) {
+ printk(BIOS_ERR,
+ "dp: failed to power on panel (0x%x)\n", ret);
+ goto error_enable;
+ }
+
+ /* Confirm DP is plugging status */
+ if (!(tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT) &
+ DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
+ printk(BIOS_ERR, "dp: could not detect HPD\n");
+ goto error_enable;
+ }
+
+ /* Check DP version */
+ if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_REV, &dp->revision))
+ printk(BIOS_ERR,
+ "dp: failed to read the revision number from sink\n");
+
+ if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, config)) {
+ printk(BIOS_ERR, "dp: error to configure link\n");
+ goto error_enable;
+ }
+
+ tegra_dc_sor_set_power_state(&dp->sor, 1);
+ tegra_dc_sor_attach(&dp->sor);
+
+ tegra_dc_dp_check_sink(dp, config);
+
+ /*
+ * Power down the unused lanes to save power
+ * (about hundreds milli-watts, varies from boards).
+ */
+ tegra_dc_sor_power_down_unused_lanes(&dp->sor);
+
+ dp->enabled = 1;
+error_enable:
+ return;
+}
+
void dp_display_startup(device_t dev)
{
struct soc_nvidia_tegra132_config *config = dev->chip_info;
struct display_controller *disp_ctrl =
(void *)config->display_controller;
+ u32 framebuffer_size_mb = config->framebuffer_size / MiB;
+ u32 framebuffer_base_mb = config->framebuffer_base / MiB;
+
+ struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE;
+ struct tegra_dc *dc = &dc_data;
+ u32 plld_rate;
+
printk(BIOS_INFO, "%s: entry: disp_ctrl: %p.\n",
__func__, disp_ctrl);
+
+ if (disp_ctrl == NULL) {
+ printk(BIOS_ERR, "Error: No dc is assigned by dt.\n");
+ return;
+ }
+
+ dc->base = (void *)disp_ctrl;
+ dc->config = config;
+ config->dc_data = dc;
+
+ /* Note dp_init may read EDID and change some config values. */
+ dp_init(config);
+
+ if (framebuffer_size_mb == 0) {
+ framebuffer_size_mb = ALIGN_UP(config->display_xres *
+ config->display_yres *
+ (config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
+ }
+
+ config->framebuffer_size = framebuffer_size_mb * MiB;
+ config->framebuffer_base = framebuffer_base_mb * MiB;
+
+ /* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
+ * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
+ * update_display_mode() for detail.
+ */
+ plld_rate = clock_configure_plld(config->pixel_clock * 2);
+ if (plld_rate == 0) {
+ printk(BIOS_ERR, "dc: clock init failed\n");
+ return;
+ } else if (plld_rate != config->pixel_clock * 2) {
+ printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate);
+ config->pixel_clock = plld_rate / 2;
+ }
+
+ /* set disp1's clock source to PLLD_OUT0 */
+ clock_configure_source(disp1, PLLD, (plld_rate/KHz)/2);
+
+ /* Init dc */
+ if (tegra_dc_init(disp_ctrl)) {
+ printk(BIOS_ERR, "dc: init failed\n");
+ return;
+ }
+
+ /* Configure dc mode */
+ if (update_display_mode(disp_ctrl, config)) {
+ printk(BIOS_ERR, "dc: failed to configure display mode.\n");
+ return;
+ }
+
+ /* Enable dp */
+ dp_enable(dc->out);
+
+ /* Set up Tegra PWM n (where n is specified in config->dp.pwm) to drive the
+ * panel backlight.
+ */
+ printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__);
+ WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) |
+ (220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */
+ 0x02e), /* frequency divider */
+ &pwm->pwm[config->dp.pwm].csr);
+
+ /* Set up window */
+ update_window(config);
+ printk(BIOS_INFO, "%s: display init done.\n", __func__);
+
+ /* Save panel mode to cb tables */
+ pass_mode_info_to_payload(config);
+
+ /*
+ * After this point, it is payload's responsibility to allocate
+ * framebuffer and sets the base address to dc's
+ * WINBUF_START_ADDR register and enables window by setting dc's
+ * DISP_DISP_WIN_OPTIONS register.
+ */
}
diff --git a/src/soc/nvidia/tegra132/include/soc/display.h b/src/soc/nvidia/tegra132/include/soc/display.h
index 7fd68b1..9066659 100644
--- a/src/soc/nvidia/tegra132/include/soc/display.h
+++ b/src/soc/nvidia/tegra132/include/soc/display.h
@@ -34,6 +34,14 @@
(mode->yres + mode->vfront_porch + \
mode->vsync_width + mode->vback_porch)
+enum {
+ /* norrin64 */
+ TEGRA_EDID_I2C_ADDRESS = 0x50,
+};
+
+/* refresh rate = 60/s */
+#define FRAME_IN_MS 17
+
/* forward declaration */
struct soc_nvidia_tegra132_config;
struct display_controller;
diff --git a/src/soc/nvidia/tegra132/include/soc/sor.h b/src/soc/nvidia/tegra132/include/soc/sor.h
new file mode 100644
index 0000000..3413af5
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/sor.h
@@ -0,0 +1,930 @@
+/*
+ * drivers/video/tegra/dc/sor_regs.h
+ *
+ * Copyright (c) 2011-2014, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __TEGRA132_SOR_H__
+#define __TEGRA132_SOR_H__
+
+#define NV_SOR_SUPER_STATE0 (0x1)
+#define NV_SOR_SUPER_STATE0_UPDATE_SHIFT (0)
+#define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK (0x1)
+#define NV_SOR_SUPER_STATE1 (0x2)
+#define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT (3)
+#define NV_SOR_SUPER_STATE1_ATTACHED_NO (0 << 3)
+#define NV_SOR_SUPER_STATE1_ATTACHED_YES (1 << 3)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT (2)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2)
+#define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT (0)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK (0x3)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP (0)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE (1)
+#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE (2)
+#define NV_SOR_STATE0 (0x3)
+#define NV_SOR_STATE0_UPDATE_SHIFT (0)
+#define NV_SOR_STATE0_UPDATE_DEFAULT_MASK (0x1)
+#define NV_SOR_STATE1 (0x4)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT (17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17)
+#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17)
+#define NV_SOR_STATE1_ASY_REPLICATE_SHIFT (15)
+#define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK (0x3 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_OFF (0 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_X2 (1 << 15)
+#define NV_SOR_STATE1_ASY_REPLICATE_X4 (2 << 15)
+#define NV_SOR_STATE1_ASY_DEPOL_SHIFT (14)
+#define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK (0x1 << 14)
+#define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14)
+#define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT (13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK (0x1 << 13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13)
+#define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT (12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK (0x1 << 12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12)
+#define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12)
+#define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT (8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DP_A (8 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_DP_B (9 << 8)
+#define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM (15 << 8)
+#define NV_SOR_STATE1_ASY_CRCMODE_SHIFT (6)
+#define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK (0x3 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6)
+#define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT (4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK (0x3 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_NONE (0 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
+#define NV_SOR_STATE1_ASY_SUBOWNER_BOTH (3 << 4)
+#define NV_SOR_STATE1_ASY_OWNER_SHIFT (0)
+#define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK (0xf)
+#define NV_SOR_STATE1_ASY_OWNER_NONE (0)
+#define NV_SOR_STATE1_ASY_OWNER_HEAD0 (1)
+#define NV_SOR_STATE1_ASY_OWNER_HEAD1 (2)
+#define NV_HEAD_STATE0(i) (0x5)
+#define NV_HEAD_STATE0_INTERLACED_SHIFT (4)
+#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (0x3 << 4)
+#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4)
+#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4)
+#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT (3)
+#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (0x1 << 3)
+#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3)
+#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3)
+#define NV_HEAD_STATE0_DYNRANGE_SHIFT (2)
+#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (0x1 << 2)
+#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2)
+#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2)
+#define NV_HEAD_STATE0_COLORSPACE_SHIFT (0)
+#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK (0x3)
+#define NV_HEAD_STATE0_COLORSPACE_RGB (0)
+#define NV_HEAD_STATE0_COLORSPACE_YUV_601 (1)
+#define NV_HEAD_STATE0_COLORSPACE_YUV_709 (2)
+#define NV_HEAD_STATE1(i) (0x7 + i)
+#define NV_HEAD_STATE1_VTOTAL_SHIFT (16)
+#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16)
+#define NV_HEAD_STATE1_HTOTAL_SHIFT (0)
+#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK (0x7fff)
+#define NV_HEAD_STATE2(i) (0x9 + i)
+#define NV_HEAD_STATE2_VSYNC_END_SHIFT (16)
+#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16)
+#define NV_HEAD_STATE2_HSYNC_END_SHIFT (0)
+#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK (0x7fff)
+#define NV_HEAD_STATE3(i) (0xb + i)
+#define NV_HEAD_STATE3_VBLANK_END_SHIFT (16)
+#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16)
+#define NV_HEAD_STATE3_HBLANK_END_SHIFT (0)
+#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK (0x7fff)
+#define NV_HEAD_STATE4(i) (0xd + i)
+#define NV_HEAD_STATE4_VBLANK_START_SHIFT (16)
+#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16)
+#define NV_HEAD_STATE4_HBLANK_START_SHIFT (0)
+#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK (0x7fff)
+#define NV_HEAD_STATE5(i) (0xf + i)
+#define NV_SOR_CRC_CNTRL (0x11)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT (0)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO (0)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_YES (1)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DIS (0)
+#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN (1)
+#define NV_SOR_CLK_CNTRL (0x13)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT (0)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK (0x3)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2)
+#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT (2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2)
+#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2)
+#define NV_SOR_CAP (0x14)
+#define NV_SOR_CAP_DP_A_SHIFT (24)
+#define NV_SOR_CAP_DP_A_DEFAULT_MASK (0x1 << 24)
+#define NV_SOR_CAP_DP_A_FALSE (0 << 24)
+#define NV_SOR_CAP_DP_A_TRUE (1 << 24)
+#define NV_SOR_CAP_DP_B_SHIFT (25)
+#define NV_SOR_CAP_DP_B_DEFAULT_MASK (0x1 << 24)
+#define NV_SOR_CAP_DP_B_FALSE (0 << 24)
+#define NV_SOR_CAP_DP_B_TRUE (1 << 24)
+#define NV_SOR_PWR (0x15)
+#define NV_SOR_PWR_SETTING_NEW_SHIFT (31)
+#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK (0x1 << 31)
+#define NV_SOR_PWR_SETTING_NEW_DONE (0 << 31)
+#define NV_SOR_PWR_SETTING_NEW_PENDING (1 << 31)
+#define NV_SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
+#define NV_SOR_PWR_MODE_SHIFT (28)
+#define NV_SOR_PWR_MODE_DEFAULT_MASK (0x1 << 28)
+#define NV_SOR_PWR_MODE_NORMAL (0 << 28)
+#define NV_SOR_PWR_MODE_SAFE (1 << 28)
+#define NV_SOR_PWR_HALT_DELAY_SHIFT (24)
+#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK (0x1 << 24)
+#define NV_SOR_PWR_HALT_DELAY_DONE (0 << 24)
+#define NV_SOR_PWR_HALT_DELAY_ACTIVE (1 << 24)
+#define NV_SOR_PWR_SAFE_START_SHIFT (17)
+#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK (0x1 << 17)
+#define NV_SOR_PWR_SAFE_START_NORMAL (0 << 17)
+#define NV_SOR_PWR_SAFE_START_ALT (1 << 17)
+#define NV_SOR_PWR_SAFE_STATE_SHIFT (16)
+#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK (0x1 << 16)
+#define NV_SOR_PWR_SAFE_STATE_PD (0 << 16)
+#define NV_SOR_PWR_SAFE_STATE_PU (1 << 16)
+#define NV_SOR_PWR_NORMAL_START_SHIFT (1)
+#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK (0x1 << 1)
+#define NV_SOR_PWR_NORMAL_START_NORMAL (0 << 16)
+#define NV_SOR_PWR_NORMAL_START_ALT (1 << 16)
+#define NV_SOR_PWR_NORMAL_STATE_SHIFT (0)
+#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK (0x1)
+#define NV_SOR_PWR_NORMAL_STATE_PD (0)
+#define NV_SOR_PWR_NORMAL_STATE_PU (1)
+#define NV_SOR_TEST (0x16)
+#define NV_SOR_TEST_TESTMUX_SHIFT (24)
+#define NV_SOR_TEST_TESTMUX_DEFAULT_MASK (0xff << 24)
+#define NV_SOR_TEST_TESTMUX_AVSS (0 << 24)
+#define NV_SOR_TEST_TESTMUX_CLOCKIN (2 << 24)
+#define NV_SOR_TEST_TESTMUX_PLL_VOL (4 << 24)
+#define NV_SOR_TEST_TESTMUX_SLOWCLKINT (8 << 24)
+#define NV_SOR_TEST_TESTMUX_AVDD (16 << 24)
+#define NV_SOR_TEST_TESTMUX_VDDREG (32 << 24)
+#define NV_SOR_TEST_TESTMUX_REGREF_VDDREG (64 << 24)
+#define NV_SOR_TEST_TESTMUX_REGREF_AVDD (128 << 24)
+#define NV_SOR_TEST_CRC_SHIFT (23)
+#define NV_SOR_TEST_CRC_PRE_SERIALIZE (0 << 23)
+#define NV_SOR_TEST_CRC_POST_DESERIALIZE (1 << 23)
+#define NV_SOR_TEST_TPAT_SHIFT (20)
+#define NV_SOR_TEST_TPAT_DEFAULT_MASK (0x7 << 20)
+#define NV_SOR_TEST_TPAT_LO (0 << 20)
+#define NV_SOR_TEST_TPAT_TDAT (1 << 20)
+#define NV_SOR_TEST_TPAT_RAMP (2 << 20)
+#define NV_SOR_TEST_TPAT_WALK (3 << 20)
+#define NV_SOR_TEST_TPAT_MAXSTEP (4 << 20)
+#define NV_SOR_TEST_TPAT_MINSTEP (5 << 20)
+#define NV_SOR_TEST_DSRC_SHIFT (16)
+#define NV_SOR_TEST_DSRC_DEFAULT_MASK (0x3 << 16)
+#define NV_SOR_TEST_DSRC_NORMAL (0 << 16)
+#define NV_SOR_TEST_DSRC_DEBUG (1 << 16)
+#define NV_SOR_TEST_DSRC_TGEN (2 << 16)
+#define NV_SOR_TEST_HEAD_NUMBER_SHIFT (12)
+#define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK (0x3 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_NONE (0 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_HEAD0 (1 << 12)
+#define NV_SOR_TEST_HEAD_NUMBER_HEAD1 (2 << 12)
+#define NV_SOR_TEST_ATTACHED_SHIFT (10)
+#define NV_SOR_TEST_ATTACHED_DEFAULT_MASK (0x1 << 10)
+#define NV_SOR_TEST_ATTACHED_FALSE (0 << 10)
+#define NV_SOR_TEST_ATTACHED_TRUE (1 << 10)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT (8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (0x3 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8)
+#define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8)
+#define NV_SOR_TEST_INVD_SHIFT (6)
+#define NV_SOR_TEST_INVD_DISABLE (0 << 6)
+#define NV_SOR_TEST_INVD_ENABLE (1 << 6)
+#define NV_SOR_TEST_TEST_ENABLE_SHIFT (1)
+#define NV_SOR_TEST_TEST_ENABLE_DISABLE (0 << 1)
+#define NV_SOR_TEST_TEST_ENABLE_ENABLE (1 << 1)
+#define NV_SOR_PLL0 (0x17)
+#define NV_SOR_PLL0_ICHPMP_SHFIT (24)
+#define NV_SOR_PLL0_ICHPMP_DEFAULT_MASK (0xf << 24)
+#define NV_SOR_PLL0_VCOCAP_SHIFT (8)
+#define NV_SOR_PLL0_VCOCAP_DEFAULT_MASK (0xf << 8)
+#define NV_SOR_PLL0_PLLREG_LEVEL_SHIFT (6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_DEFAULT_MASK (0x3 << 6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_V25 (0 << 6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_V15 (1 << 6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_V35 (2 << 6)
+#define NV_SOR_PLL0_PLLREG_LEVEL_V45 (3 << 6)
+#define NV_SOR_PLL0_PULLDOWN_SHIFT (5)
+#define NV_SOR_PLL0_PULLDOWN_DEFAULT_MASK (0x1 << 5)
+#define NV_SOR_PLL0_PULLDOWN_DISABLE (0 << 5)
+#define NV_SOR_PLL0_PULLDOWN_ENABLE (1 << 5)
+#define NV_SOR_PLL0_RESISTORSEL_SHIFT (4)
+#define NV_SOR_PLL0_RESISTORSEL_DEFAULT_MASK (0x1 << 4)
+#define NV_SOR_PLL0_RESISTORSEL_INT (0 << 4)
+#define NV_SOR_PLL0_RESISTORSEL_EXT (1 << 4)
+#define NV_SOR_PLL0_VCOPD_SHIFT (2)
+#define NV_SOR_PLL0_VCOPD_MASK (1 << 2)
+#define NV_SOR_PLL0_VCOPD_RESCIND (0 << 2)
+#define NV_SOR_PLL0_VCOPD_ASSERT (1 << 2)
+#define NV_SOR_PLL0_PWR_SHIFT (0)
+#define NV_SOR_PLL0_PWR_MASK (1)
+#define NV_SOR_PLL0_PWR_ON (0)
+#define NV_SOR_PLL0_PWR_OFF (1)
+#define NV_SOR_PLL1_TMDS_TERM_SHIFT (8)
+#define NV_SOR_PLL1_TMDS_TERM_DISABLE (0 << 8)
+#define NV_SOR_PLL1_TMDS_TERM_ENABLE (1 << 8)
+#define NV_SOR_PLL1 (0x18)
+#define NV_SOR_PLL1_TERM_COMPOUT_SHIFT (15)
+#define NV_SOR_PLL1_TERM_COMPOUT_LOW (0 << 15)
+#define NV_SOR_PLL1_TERM_COMPOUT_HIGH (1 << 15)
+#define NV_SOR_PLL2 (0x19)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT (0)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0)
+#define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW (1 << 0)
+#define NV_SOR_PLL2_AUX1_SHIFT (17)
+#define NV_SOR_PLL2_AUX1_SEQ_MASK (1 << 17)
+#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17)
+#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17)
+#define NV_SOR_PLL2_AUX2_SHIFT (18)
+#define NV_SOR_PLL2_AUX2_MASK (1 << 18)
+#define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18)
+#define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN (1 << 18)
+#define NV_SOR_PLL2_AUX6_SHIFT (22)
+#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22)
+#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22)
+#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22)
+#define NV_SOR_PLL2_AUX7_SHIFT (23)
+#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23)
+#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23)
+#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23)
+#define NV_SOR_PLL2_AUX8_SHIFT (24)
+#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24)
+#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24)
+#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24)
+#define NV_SOR_PLL2_AUX9_SHIFT (25)
+#define NV_SOR_PLL2_AUX9_LVDSEN_ALLOW (0 << 25)
+#define NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25)
+#define NV_SOR_PLL3 (0x1a)
+#define NV_SOR_PLL3_PLLVDD_MODE_SHIFT (13)
+#define NV_SOR_PLL3_PLLVDD_MODE_MASK (1 << 13)
+#define NV_SOR_PLL3_PLLVDD_MODE_V1_8 (0 << 13)
+#define NV_SOR_PLL3_PLLVDD_MODE_V3_3 (1 << 13)
+#define NV_SOR_CSTM (0x1b)
+#define NV_SOR_CSTM_ROTDAT_SHIFT (28)
+#define NV_SOR_CSTM_ROTDAT_DEFAULT_MASK (0x7 << 28)
+#define NV_SOR_CSTM_ROTCLK_SHIFT (24)
+#define NV_SOR_CSTM_ROTCLK_DEFAULT_MASK (0xf << 24)
+#define NV_SOR_CSTM_LVDS_EN_SHIFT (16)
+#define NV_SOR_CSTM_LVDS_EN_DISABLE (0 << 16)
+#define NV_SOR_CSTM_LVDS_EN_ENABLE (1 << 16)
+#define NV_SOR_CSTM_LINKACTB_SHIFT (15)
+#define NV_SOR_CSTM_LINKACTB_DISABLE (0 << 15)
+#define NV_SOR_CSTM_LINKACTB_ENABLE (1 << 15)
+#define NV_SOR_CSTM_LINKACTA_SHIFT (14)
+#define NV_SOR_CSTM_LINKACTA_DISABLE (0 << 14)
+#define NV_SOR_CSTM_LINKACTA_ENABLE (1 << 14)
+#define NV_SOR_LVDS (0x1c)
+#define NV_SOR_LVDS_ROTDAT_SHIFT (28)
+#define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK (0x7 << 28)
+#define NV_SOR_LVDS_ROTDAT_RST (0 << 28)
+#define NV_SOR_LVDS_ROTCLK_SHIFT (24)
+#define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK (0xf << 24)
+#define NV_SOR_LVDS_ROTCLK_RST (0 << 24)
+#define NV_SOR_LVDS_PLLDIV_SHIFT (21)
+#define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK (0x1 << 21)
+#define NV_SOR_LVDS_PLLDIV_BY_7 (0 << 21)
+#define NV_SOR_LVDS_BALANCED_SHIFT (19)
+#define NV_SOR_LVDS_BALANCED_DEFAULT_MASK (0x1 << 19)
+#define NV_SOR_LVDS_BALANCED_DISABLE (0 << 19)
+#define NV_SOR_LVDS_BALANCED_ENABLE (1 << 19)
+#define NV_SOR_LVDS_NEW_MODE_SHIFT (18)
+#define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK (0x1 << 18)
+#define NV_SOR_LVDS_NEW_MODE_DISABLE (0 << 18)
+#define NV_SOR_LVDS_NEW_MODE_ENABLE (1 << 18)
+#define NV_SOR_LVDS_DUP_SYNC_SHIFT (17)
+#define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK (0x1 << 17)
+#define NV_SOR_LVDS_DUP_SYNC_DISABLE (0 << 17)
+#define NV_SOR_LVDS_DUP_SYNC_ENABLE (1 << 17)
+#define NV_SOR_LVDS_LVDS_EN_SHIFT (16)
+#define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK (0x1 << 16)
+#define NV_SOR_LVDS_LVDS_EN_ENABLE (1 << 16)
+#define NV_SOR_LVDS_LINKACTB_SHIFT (15)
+#define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK (0x1 << 15)
+#define NV_SOR_LVDS_LINKACTB_DISABLE (0 << 15)
+#define NV_SOR_LVDS_LINKACTB_ENABLE (1 << 15)
+#define NV_SOR_LVDS_LINKACTA_SHIFT (14)
+#define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK (0x1 << 14)
+#define NV_SOR_LVDS_LINKACTA_ENABLE (1 << 14)
+#define NV_SOR_LVDS_MODE_SHIFT (12)
+#define NV_SOR_LVDS_MODE_DEFAULT_MASK (0x3 << 12)
+#define NV_SOR_LVDS_MODE_LVDS (0 << 12)
+#define NV_SOR_LVDS_UPPER_SHIFT (11)
+#define NV_SOR_LVDS_UPPER_DEFAULT_MASK (0x1 << 11)
+#define NV_SOR_LVDS_UPPER_FALSE (0 << 11)
+#define NV_SOR_LVDS_UPPER_TRUE (1 << 11)
+#define NV_SOR_LVDS_PD_TXCB_SHIFT (9)
+#define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK (0x1 << 9)
+#define NV_SOR_LVDS_PD_TXCB_ENABLE (0 << 9)
+#define NV_SOR_LVDS_PD_TXCB_DISABLE (1 << 9)
+#define NV_SOR_LVDS_PD_TXCA_SHIFT (8)
+#define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK (0x1 << 8)
+#define NV_SOR_LVDS_PD_TXCA_ENABLE (0 << 8)
+#define NV_SOR_LVDS_PD_TXDB_3_SHIFT (7)
+#define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK (0x1 << 7)
+#define NV_SOR_LVDS_PD_TXDB_3_ENABLE (0 << 7)
+#define NV_SOR_LVDS_PD_TXDB_3_DISABLE (1 << 7)
+#define NV_SOR_LVDS_PD_TXDB_2_SHIFT (6)
+#define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK (0x1 << 6)
+#define NV_SOR_LVDS_PD_TXDB_2_ENABLE (0 << 6)
+#define NV_SOR_LVDS_PD_TXDB_2_DISABLE (1 << 6)
+#define NV_SOR_LVDS_PD_TXDB_1_SHIFT (5)
+#define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK (0x1 << 5)
+#define NV_SOR_LVDS_PD_TXDB_1_ENABLE (0 << 5)
+#define NV_SOR_LVDS_PD_TXDB_1_DISABLE (1 << 5)
+#define NV_SOR_LVDS_PD_TXDB_0_SHIFT (4)
+#define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK (0x1 << 4)
+#define NV_SOR_LVDS_PD_TXDB_0_ENABLE (0 << 4)
+#define NV_SOR_LVDS_PD_TXDB_0_DISABLE (1 << 4)
+#define NV_SOR_LVDS_PD_TXDA_3_SHIFT (3)
+#define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK (0x1 << 3)
+#define NV_SOR_LVDS_PD_TXDA_3_ENABLE (0 << 3)
+#define NV_SOR_LVDS_PD_TXDA_3_DISABLE (1 << 3)
+#define NV_SOR_LVDS_PD_TXDA_2_SHIFT (2)
+#define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK (0x1 << 2)
+#define NV_SOR_LVDS_PD_TXDA_2_ENABLE (0 << 2)
+#define NV_SOR_LVDS_PD_TXDA_1_SHIFT (1)
+#define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK (0x1 << 1)
+#define NV_SOR_LVDS_PD_TXDA_1_ENABLE (0 << 1)
+#define NV_SOR_LVDS_PD_TXDA_0_SHIFT (0)
+#define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK (0x1)
+#define NV_SOR_LVDS_PD_TXDA_0_ENABLE (0)
+#define NV_SOR_CRCA (0x1d)
+#define NV_SOR_CRCA_VALID_FALSE (0)
+#define NV_SOR_CRCA_VALID_TRUE (1)
+#define NV_SOR_CRCA_VALID_RST (1)
+#define NV_SOR_CRCB (0x1e)
+#define NV_SOR_CRCB_CRC_DEFAULT_MASK (0xffffffff)
+#define NV_SOR_SEQ_CTL (0x20)
+#define NV_SOR_SEQ_CTL_SWITCH_SHIFT (30)
+#define NV_SOR_SEQ_CTL_SWITCH_MASK (0x1 << 30)
+#define NV_SOR_SEQ_CTL_SWITCH_WAIT (0 << 30)
+#define NV_SOR_SEQ_CTL_SWITCH_FORCE (1 << 30)
+#define NV_SOR_SEQ_CTL_STATUS_SHIFT (28)
+#define NV_SOR_SEQ_CTL_STATUS_MASK (0x1 << 28)
+#define NV_SOR_SEQ_CTL_STATUS_STOPPED (0 << 28)
+#define NV_SOR_SEQ_CTL_STATUS_RUNNING (1 << 28)
+#define NV_SOR_SEQ_CTL_PC_SHIFT (16)
+#define NV_SOR_SEQ_CTL_PC_MASK (0xf << 16)
+#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT (12)
+#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK (0xf << 12)
+#define NV_SOR_SEQ_CTL_PD_PC_SHIFT (8)
+#define NV_SOR_SEQ_CTL_PD_PC_MASK (0xf << 8)
+#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT (4)
+#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK (0xf << 4)
+#define NV_SOR_SEQ_CTL_PU_PC_SHIFT (0)
+#define NV_SOR_SEQ_CTL_PU_PC_MASK (0xf)
+#define NV_SOR_LANE_SEQ_CTL (0x21)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT (31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT (28)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28)
+#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT (20)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20)
+#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT (16)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16)
+#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16)
+#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT (12)
+#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT (9)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9)
+#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT (8)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8)
+#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT (7)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7)
+#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT (6)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6)
+#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT (5)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5)
+#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT (4)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4)
+#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT (3)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3)
+#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT (2)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2)
+#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT (1)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1)
+#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT (0)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP (0)
+#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN (1)
+#define NV_SOR_SEQ_INST(i) (0x22 + i)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT (31)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31)
+#define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT (30)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30)
+#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT (29)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29)
+#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29)
+#define NV_SOR_SEQ_INST_BLANK_V_SHIFT (28)
+#define NV_SOR_SEQ_INST_BLANK_V_NORMAL (0 << 28)
+#define NV_SOR_SEQ_INST_BLANK_V_INACTIVE (1 << 28)
+#define NV_SOR_SEQ_INST_BLANK_H_SHIFT (27)
+#define NV_SOR_SEQ_INST_BLANK_H_NORMAL (0 << 27)
+#define NV_SOR_SEQ_INST_BLANK_H_INACTIVE (1 << 27)
+#define NV_SOR_SEQ_INST_BLANK_DE_SHIFT (26)
+#define NV_SOR_SEQ_INST_BLANK_DE_NORMAL (0 << 26)
+#define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE (1 << 26)
+#define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT (25)
+#define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL (0 << 25)
+#define NV_SOR_SEQ_INST_BLACK_DATA_BLACK (1 << 25)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT (24)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24)
+#define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT (23)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23)
+#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23)
+#define NV_SOR_SEQ_INST_PIN_B_SHIFT (22)
+#define NV_SOR_SEQ_INST_PIN_B_LOW (0 << 22)
+#define NV_SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
+#define NV_SOR_SEQ_INST_PIN_A_SHIFT (21)
+#define NV_SOR_SEQ_INST_PIN_A_LOW (0 << 21)
+#define NV_SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
+#define NV_SOR_SEQ_INST_SEQUENCE_SHIFT (19)
+#define NV_SOR_SEQ_INST_SEQUENCE_UP (0 << 19)
+#define NV_SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19)
+#define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT (18)
+#define NV_SOR_SEQ_INST_LANE_SEQ_STOP (0 << 18)
+#define NV_SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18)
+#define NV_SOR_SEQ_INST_PDPORT_SHIFT (17)
+#define NV_SOR_SEQ_INST_PDPORT_NO (0 << 17)
+#define NV_SOR_SEQ_INST_PDPORT_YES (1 << 17)
+#define NV_SOR_SEQ_INST_PDPLL_SHIFT (16)
+#define NV_SOR_SEQ_INST_PDPLL_NO (0 << 16)
+#define NV_SOR_SEQ_INST_PDPLL_YES (1 << 16)
+#define NV_SOR_SEQ_INST_HALT_SHIFT (15)
+#define NV_SOR_SEQ_INST_HALT_FALSE (0 << 15)
+#define NV_SOR_SEQ_INST_HALT_TRUE (1 << 15)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT (12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK (0x3 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_US (0 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_MS (1 << 12)
+#define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
+#define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT (0)
+#define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK (0x3ff)
+#define NV_SOR_PWM_DIV (0x32)
+#define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK (0xffffff)
+#define NV_SOR_PWM_CTL (0x33)
+#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT (31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_DONE (0 << 31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING (1 << 31)
+#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER (1 << 31)
+#define NV_SOR_PWM_CTL_CLKSEL_SHIFT (30)
+#define NV_SOR_PWM_CTL_CLKSEL_PCLK (0 << 30)
+#define NV_SOR_PWM_CTL_CLKSEL_XTAL (1 << 30)
+#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT (0)
+#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK (0xffffff)
+#define NV_SOR_MSCHECK (0x49)
+#define NV_SOR_MSCHECK_CTL_SHIFT (31)
+#define NV_SOR_MSCHECK_CTL_CLEAR (0 << 31)
+#define NV_SOR_MSCHECK_CTL_RUN (1 << 31)
+#define NV_SOR_XBAR_CTRL (0x4a)
+#define NV_SOR_DP_LINKCTL(i) (0x4c + (i))
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT (31)
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31)
+#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT (28)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28)
+#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT (16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK (0x1f << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO (0 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE (1 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO (3 << 16)
+#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR (15 << 16)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT (14)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14)
+#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT (10)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE (0 << 10)
+#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE (1 << 10)
+#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT (2)
+#define NV_SOR_DP_LINKCTL_TUSIZE_MASK (0x7f << 2)
+#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT (0)
+#define NV_SOR_DP_LINKCTL_ENABLE_NO (0)
+#define NV_SOR_DP_LINKCTL_ENABLE_YES (1)
+#define NV_SOR_DC(i) (0x4e + (i))
+#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT (24)
+#define NV_SOR_DC_LANE3_DP_LANE3_MASK (0xff << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24)
+#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT (16)
+#define NV_SOR_DC_LANE2_DP_LANE0_MASK (0xff << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16)
+#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT (8)
+#define NV_SOR_DC_LANE1_DP_LANE1_MASK (0xff << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8)
+#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT (0)
+#define NV_SOR_DC_LANE0_DP_LANE2_MASK (0xff)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0 (17)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0 (21)
+#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0 (26)
+#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0 (34)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1 (26)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1 (32)
+#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1 (39)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2 (34)
+#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2 (43)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3 (51)
+#define NV_SOR_LANE_DRIVE_CURRENT(i) (0x4e + (i))
+#define NV_SOR_PR(i) (0x52 + (i))
+#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT (24)
+#define NV_SOR_PR_LANE3_DP_LANE3_MASK (0xff << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24)
+#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24)
+#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT (16)
+#define NV_SOR_PR_LANE2_DP_LANE0_MASK (0xff << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16)
+#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16)
+#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT (8)
+#define NV_SOR_PR_LANE1_DP_LANE1_MASK (0xff >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8)
+#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8)
+#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_MASK (0xff)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0 (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0 (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0 (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0 (0)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1 (4)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1 (6)
+#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1 (17)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2 (8)
+#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2 (13)
+#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3 (17)
+#define NV_SOR_LANE4_PREEMPHASIS(i) (0x54 + (i))
+#define NV_SOR_POSTCURSOR(i) (0x56 + (i))
+#define NV_SOR_DP_CONFIG(i) (0x58 + (i))
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT (31)
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31)
+#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT (28)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28)
+#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT (26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT (24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT (16)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT (8)
+#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8)
+#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT (0)
+#define NV_SOR_DP_CONFIG_WATERMARK_MASK (0x3f)
+#define NV_SOR_DP_MN(i) (0x5a + i)
+#define NV_SOR_DP_MN_M_MOD_SHIFT (30)
+#define NV_SOR_DP_MN_M_MOD_DEFAULT_MASK (0x3 << 30)
+#define NV_SOR_DP_MN_M_MOD_NONE (0 << 30)
+#define NV_SOR_DP_MN_M_MOD_INC (1 << 30)
+#define NV_SOR_DP_MN_M_MOD_DEC (2 << 30)
+#define NV_SOR_DP_MN_M_DELTA_SHIFT (24)
+#define NV_SOR_DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24)
+#define NV_SOR_DP_MN_N_VAL_SHIFT (0)
+#define NV_SOR_DP_MN_N_VAL_DEFAULT_MASK (0xffffff)
+#define NV_SOR_DP_PADCTL(i) (0x5c + (i))
+#define NV_SOR_DP_PADCTL_SPARE_SHIFT (25)
+#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25)
+#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT (24)
+#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE (0 << 24)
+#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE (1 << 24)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT (23)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23)
+#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23)
+#define NV_SOR_DP_PADCTL_TX_PU_SHIFT (22)
+#define NV_SOR_DP_PADCTL_TX_PU_DISABLE (0 << 22)
+#define NV_SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22)
+#define NV_SOR_DP_PADCTL_TX_PU_MASK (1 << 22)
+#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT (20)
+#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK (0x3 << 20)
+#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT (16)
+#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE (0 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX (1 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16)
+#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16)
+#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT (8)
+#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT (7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT (6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT (5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT (4)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4)
+#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT (3)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_YES (0 << 3)
+#define NV_SOR_DP_PADCTL_PD_TXD_3_NO (1 << 3)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT (2)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_YES (0 << 2)
+#define NV_SOR_DP_PADCTL_PD_TXD_0_NO (1 << 2)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT (1)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_YES (0 << 1)
+#define NV_SOR_DP_PADCTL_PD_TXD_1_NO (1 << 1)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT (0)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_YES (0)
+#define NV_SOR_DP_PADCTL_PD_TXD_2_NO (1)
+#define NV_SOR_DP_DEBUG(i) (0x5e + i)
+#define NV_SOR_DP_SPARE(i) (0x60 + (i))
+#define NV_SOR_DP_SPARE_REG_SHIFT (3)
+#define NV_SOR_DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT (2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (0x1 << 2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2)
+#define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2)
+#define NV_SOR_DP_SPARE_PANEL_SHIFT (1)
+#define NV_SOR_DP_SPARE_PANEL_EXTERNAL (0 << 1)
+#define NV_SOR_DP_SPARE_PANEL_INTERNAL (1 << 1)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT (0)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO (0)
+#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES (1)
+#define NV_SOR_DP_AUDIO_CTRL (0x62)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS (0x63)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x1ffff)
+#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT (0)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS (0x64)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1ffff)
+#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT (0)
+#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER (0x65)
+#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i))
+#define NV_SOR_DP_TPG (0x6d)
+#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_SHIFT (30)
+#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30)
+#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30)
+#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_SHIFT (28)
+#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28)
+#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_SHIFT (24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_D102 (4 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_CSTM (7 << 24)
+#define NV_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24)
+#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_SHIFT (22)
+#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22)
+#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_SHIFT (20)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (0x3 << 20)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20)
+#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_SHIFT (16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_D102 (4 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_CSTM (7 << 16)
+#define NV_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16)
+#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_SHIFT (14)
+#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14)
+#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_SHIFT (12)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (0x3 << 12)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12)
+#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT (8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_D102 (4 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_CSTM (7 << 8)
+#define NV_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8)
+#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT (6)
+#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6)
+#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT (4)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (0x3 << 4)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4)
+#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_SHIFT (0)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_DEFAULT_MASK (0xf)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN (0)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING1 (1)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING2 (2)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING3 (3)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_D102 (4)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE (5)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_PRBS7 (6)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_CSTM (7)
+#define NV_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE (8)
+
+enum {
+ training_pattern_disabled = 0,
+ training_pattern_1 = 1,
+ training_pattern_2 = 2,
+ training_pattern_3 = 3,
+ training_pattern_none = 0xff
+};
+
+enum tegra_dc_sor_protocol {
+ SOR_DP,
+ SOR_LVDS,
+};
+
+#define SOR_LINK_SPEED_G1_62 6
+#define SOR_LINK_SPEED_G2_7 10
+#define SOR_LINK_SPEED_G5_4 20
+#define SOR_LINK_SPEED_LVDS 7
+
+/* todo: combine this and the intel_dp struct into one struct. */
+struct tegra_dc_dp_link_config {
+ int is_valid;
+
+ /* Supported configuration */
+ u8 max_link_bw;
+ u8 max_lane_count;
+ int downspread;
+ int support_enhanced_framing;
+ u32 bits_per_pixel;
+ int alt_scramber_reset_cap; /* true for eDP */
+ int only_enhanced_framing; /* enhanced_frame_en ignored */
+
+ /* Actual configuration */
+ u8 link_bw;
+ u8 lane_count;
+ int enhanced_framing;
+ int scramble_ena;
+
+ u32 activepolarity;
+ u32 active_count;
+ u32 tu_size;
+ u32 active_frac;
+ u32 watermark;
+
+ s32 hblank_sym;
+ s32 vblank_sym;
+
+ /* Training data */
+ u32 drive_current;
+ u32 preemphasis;
+ u32 postcursor;
+ u8 aux_rd_interval;
+ u8 tps3_supported;
+};
+
+/* TODO: just pull these up into one struct? Need to see how this impacts
+ * having two channels.
+ */
+struct tegra_dc_sor_data {
+ struct tegra_dc *dc;
+ void *base;
+ void *pmc_base;
+ u8 portnum; /* 0 or 1 */
+ struct tegra_dc_dp_link_config *link_cfg;
+ int power_is_up;
+};
+
+#define TEGRA_SOR_TIMEOUT_MS 1000
+#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000
+#define TEGRA_DC_POLL_TIMEOUT_MS 50
+
+#define CHECK_RET(x) \
+ do { \
+ ret = (x); \
+ if (ret != 0) \
+ return ret; \
+ } while (0)
+
+void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor);
+int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd);
+void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
+ u8 training_pattern, const struct tegra_dc_dp_link_config *link_cfg);
+void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw);
+void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count);
+void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
+ int power_up);
+void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int);
+void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
+ u8 *lane_count);
+void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor);
+void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
+ const struct tegra_dc_dp_link_config *link_cfg);
+void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor);
+void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor);
+void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor);
+void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor);
+void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,
+ u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported);
+void tegra_dc_detach(struct tegra_dc_sor_data *sor);
+#endif /*__TEGRA132_SOR_H__ */
diff --git a/src/soc/nvidia/tegra132/sor.c b/src/soc/nvidia/tegra132/sor.c
new file mode 100644
index 0000000..baa0685
--- /dev/null
+++ b/src/soc/nvidia/tegra132/sor.c
@@ -0,0 +1,1100 @@
+/*
+ * drivers/video/tegra/dc/sor.c
+ *
+ * Copyright (c) 2011-2015, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <lib.h>
+#include <stdlib.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <device/device.h>
+#include <stdlib.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <cbmem.h>
+#include <soc/nvidia/tegra/dc.h>
+#include <soc/nvidia/tegra/types.h>
+#include <soc/sor.h>
+#include <soc/nvidia/tegra/displayport.h>
+#include <soc/clk_rst.h>
+#include <soc/clock.h>
+#include "chip.h"
+#include <soc/display.h>
+
+#define DEBUG_SOR 0
+
+#define APBDEV_PMC_DPD_SAMPLE (0x20)
+#define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE (0)
+#define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE (1)
+#define APBDEV_PMC_SEL_DPD_TIM (0x1c8)
+#define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT (0x7f)
+#define APBDEV_PMC_IO_DPD2_REQ (0x1c0)
+#define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT (25)
+#define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25)
+#define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT (30)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30)
+#define APBDEV_PMC_IO_DPD2_STATUS (0x1c4)
+#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT (25)
+#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25)
+#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25)
+
+#define DC_N_WINDOWS 5
+
+static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
+{
+ void *addr = sor->base + (u32) (reg << 2);
+ u32 reg_val = READL(addr);
+ return reg_val;
+}
+
+static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
+ u32 reg, u32 val)
+{
+ void *addr = sor->base + (u32) (reg << 2);
+ WRITEL(val, addr);
+}
+
+static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
+ u32 reg, u32 mask, u32 val)
+{
+ u32 reg_val = tegra_sor_readl(sor, reg);
+ reg_val &= ~mask;
+ reg_val |= val;
+ tegra_sor_writel(sor, reg, reg_val);
+}
+
+void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor)
+{
+ tegra_sor_write_field(sor,
+ NV_SOR_DP_PADCTL(sor->portnum),
+ NV_SOR_DP_PADCTL_TX_PU_MASK,
+ NV_SOR_DP_PADCTL_TX_PU_DISABLE);
+}
+
+void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,
+ u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported)
+{
+ tegra_sor_write_field(sor, NV_SOR_PR(sor->portnum),
+ mask, pe_reg);
+ tegra_sor_write_field(sor, NV_SOR_DC(sor->portnum),
+ mask, vs_reg);
+ if (pc_supported) {
+ tegra_sor_write_field(
+ sor, NV_SOR_POSTCURSOR(sor->portnum),
+ mask, pc_reg);
+ }
+}
+
+static u32 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
+ u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
+{
+ u32 temp = timeout_us;
+ u32 reg_val = 0;
+
+ do {
+ udelay(poll_interval_us);
+ reg_val = tegra_sor_readl(sor, reg);
+ if (timeout_us > poll_interval_us)
+ timeout_us -= poll_interval_us;
+ else
+ break;
+ } while ((reg_val & mask) != exp_val);
+
+ if ((reg_val & mask) == exp_val)
+ return 0; /* success */
+ printk(BIOS_ERR,
+ "sor_poll_register 0x%x: timeout, "
+ "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
+ reg, reg_val, mask, exp_val);
+
+ return temp;
+}
+
+int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
+{
+ u32 reg_val;
+ u32 orig_val;
+
+ orig_val = tegra_sor_readl(sor, NV_SOR_PWR);
+
+ reg_val = pu_pd ? NV_SOR_PWR_NORMAL_STATE_PU :
+ NV_SOR_PWR_NORMAL_STATE_PD; /* normal state only */
+
+ if (reg_val == orig_val)
+ return 0; /* No update needed */
+
+ reg_val |= NV_SOR_PWR_SETTING_NEW_TRIGGER;
+ tegra_sor_writel(sor, NV_SOR_PWR, reg_val);
+
+ /* Poll to confirm it is done */
+ if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR,
+ NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK,
+ NV_SOR_PWR_SETTING_NEW_DONE,
+ 100, TEGRA_SOR_TIMEOUT_MS * 1000)) {
+ printk(BIOS_ERR,
+ "dc timeout waiting for SOR_PWR = NEW_DONE\n");
+ return -EFAULT;
+ }
+ return 0;
+}
+
+void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
+ u8 training_pattern, const struct tegra_dc_dp_link_config *link_cfg)
+{
+ u32 reg_val;
+
+ reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
+
+ if (ena)
+ reg_val |= NV_SOR_DP_LINKCTL_ENABLE_YES;
+ else
+ reg_val &= NV_SOR_DP_LINKCTL_ENABLE_NO;
+
+ reg_val &= ~NV_SOR_DP_LINKCTL_TUSIZE_MASK;
+ reg_val |= (link_cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT);
+
+ if (link_cfg->enhanced_framing)
+ reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE;
+
+ tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
+
+ switch (training_pattern) {
+ case training_pattern_1:
+ tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141);
+ break;
+ case training_pattern_2:
+ case training_pattern_3:
+ reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
+ 0x43434343 : 0x42424242;
+ tegra_sor_writel(sor, NV_SOR_DP_TPG, reg_val);
+ break;
+ default:
+ tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050);
+ break;
+ }
+}
+
+static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
+ int pu, int is_lvds)
+{
+ u32 reg_val;
+
+ /* SOR lane sequencer */
+ if (pu)
+ reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
+ NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
+ NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU;
+ else
+ reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
+ NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP |
+ NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD;
+
+ if (is_lvds)
+ reg_val |= 15 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
+ else
+ reg_val |= 1 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT;
+
+ tegra_sor_writel(sor, NV_SOR_LANE_SEQ_CTL, reg_val);
+
+ if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL,
+ NV_SOR_LANE_SEQ_CTL_SETTING_MASK,
+ NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE,
+ 100, TEGRA_SOR_TIMEOUT_MS*1000)) {
+ printk(BIOS_ERR,
+ "dp: timeout while waiting for SOR lane sequencer "
+ "to power down langes\n");
+ return -1;
+ }
+ return 0;
+}
+
+static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
+ u32 lane_count, int pu)
+{
+ u32 reg_val;
+
+ reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum));
+
+ if (pu) {
+ switch (lane_count) {
+ case 4:
+ reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
+ NV_SOR_DP_PADCTL_PD_TXD_2_NO);
+ /* fall through */
+ case 2:
+ reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
+ case 1:
+ reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
+ break;
+ default:
+ printk(BIOS_ERR,
+ "dp: invalid lane number %d\n", lane_count);
+ return -1;
+ }
+
+ tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
+ tegra_dc_sor_set_lane_count(sor, lane_count);
+ }
+ return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
+}
+
+void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
+ int power_up)
+{
+ u32 reg_val;
+
+ reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum));
+
+ if (power_up)
+ reg_val &= ~NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN;
+ else
+ reg_val |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN;
+
+ tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
+}
+
+static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
+ u32 pwm_dutycycle)
+{
+ tegra_sor_writel(sor, NV_SOR_PWM_DIV, pwm_div);
+ tegra_sor_writel(sor, NV_SOR_PWM_CTL,
+ (pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK) |
+ NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER);
+
+ if (tegra_dc_sor_poll_register(sor, NV_SOR_PWM_CTL,
+ NV_SOR_PWM_CTL_SETTING_NEW_SHIFT,
+ NV_SOR_PWM_CTL_SETTING_NEW_DONE,
+ 100, TEGRA_SOR_TIMEOUT_MS * 1000)) {
+ printk(BIOS_ERR,
+ "dp: timeout while waiting for SOR PWM setting\n");
+ }
+}
+
+static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
+ const struct tegra_dc_dp_link_config *link_cfg)
+{
+ u32 reg_val;
+
+ tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
+
+ tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
+ reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum));
+ reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK;
+ reg_val |= link_cfg->watermark;
+ reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK;
+ reg_val |= (link_cfg->active_count <<
+ NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
+ reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK;
+ reg_val |= (link_cfg->active_frac <<
+ NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
+ if (link_cfg->activepolarity)
+ reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
+ else
+ reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
+ reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
+ NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE);
+
+ tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val);
+
+ /* program h/vblank sym */
+ tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
+ NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym);
+
+ tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS,
+ NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, link_cfg->vblank_sym);
+}
+
+static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
+{
+ tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
+ tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 1);
+ tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0);
+}
+
+static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
+{
+ tegra_sor_writel(sor, NV_SOR_STATE0, 0);
+ tegra_sor_writel(sor, NV_SOR_STATE0, 1);
+ tegra_sor_writel(sor, NV_SOR_STATE0, 0);
+}
+
+static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
+{
+ u32 reg_val;
+ void *pmc_base = sor->pmc_base;
+
+ if (up) {
+ WRITEL(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
+ pmc_base + APBDEV_PMC_DPD_SAMPLE);
+ WRITEL(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
+ }
+
+ reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
+ reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
+ APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
+
+ reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
+ APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
+ APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
+ APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
+
+ WRITEL(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
+
+ /* Polling */
+ u32 temp = 10*1000;
+ do {
+ udelay(20);
+ reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
+ if (temp > 20)
+ temp -= 20;
+ else
+ break;
+ } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
+
+ if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0)
+ printk(BIOS_ERR,
+ "PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
+
+ if (up)
+ WRITEL(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
+ pmc_base + APBDEV_PMC_DPD_SAMPLE);
+}
+
+void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
+{
+ u32 reg_val;
+
+ reg_val = tegra_sor_readl(sor, NV_SOR_DP_SPARE(sor->portnum));
+ if (is_int)
+ reg_val |= NV_SOR_DP_SPARE_PANEL_INTERNAL;
+ else
+ reg_val &= ~NV_SOR_DP_SPARE_PANEL_INTERNAL;
+
+ reg_val |= NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
+ NV_SOR_DP_SPARE_SEQ_ENABLE_YES;
+ tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum), reg_val);
+}
+
+void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
+ u8 *lane_count)
+{
+ u32 reg_val;
+
+ reg_val = tegra_sor_readl(sor, NV_SOR_CLK_CNTRL);
+ *link_bw = (reg_val & NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK)
+ >> NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT;
+ reg_val = tegra_sor_readl(sor,
+ NV_SOR_DP_LINKCTL(sor->portnum));
+
+ switch (reg_val & NV_SOR_DP_LINKCTL_LANECOUNT_MASK) {
+ case NV_SOR_DP_LINKCTL_LANECOUNT_ZERO:
+ *lane_count = 0;
+ break;
+ case NV_SOR_DP_LINKCTL_LANECOUNT_ONE:
+ *lane_count = 1;
+ break;
+ case NV_SOR_DP_LINKCTL_LANECOUNT_TWO:
+ *lane_count = 2;
+ break;
+ case NV_SOR_DP_LINKCTL_LANECOUNT_FOUR:
+ *lane_count = 4;
+ break;
+ default:
+ printk(BIOS_ERR, "Unknown lane count\n");
+ }
+}
+
+void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
+{
+ tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
+ NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK,
+ link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT);
+}
+
+void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
+{
+ u32 reg_val;
+
+ reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum));
+ reg_val &= ~NV_SOR_DP_LINKCTL_LANECOUNT_MASK;
+ switch (lane_count) {
+ case 0:
+ break;
+ case 1:
+ reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_ONE;
+ break;
+ case 2:
+ reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_TWO;
+ break;
+ case 4:
+ reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_FOUR;
+ break;
+ default:
+ /* 0 should be handled earlier. */
+ printk(BIOS_ERR, "dp: Invalid lane count %d\n",
+ lane_count);
+ return;
+ }
+ tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val);
+}
+
+static void tegra_sor_enable_edp_clock(struct tegra_dc_sor_data *sor)
+{
+ sor_clock_start();
+}
+
+/* The SOR power sequencer does not work for t124/T132 so SW has to
+ go through the power sequence manually */
+/* Power up steps from spec: */
+/* STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL */
+/* 1 1 1 1 1 1 1 1 */
+/* 2 1 1 1 1 1 0 1 */
+/* 3 1 1 0 1 1 0 1 */
+/* 4 1 0 0 0 0 0 1 */
+/* 5 0 0 0 0 0 0 1 */
+static void tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor,
+ int is_lvds)
+{
+ if (sor->power_is_up)
+ return;
+
+ /* Set link bw */
+ tegra_dc_sor_set_link_bandwidth(sor,
+ is_lvds ? NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS :
+ NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62);
+
+ /* step 1 */
+ tegra_sor_write_field(sor, NV_SOR_PLL2,
+ NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
+ NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
+ NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
+ NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE |
+ NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
+ NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
+ tegra_sor_write_field(sor, NV_SOR_PLL0,
+ NV_SOR_PLL0_PWR_MASK | /* PDPLL */
+ NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
+ NV_SOR_PLL0_PWR_OFF |
+ NV_SOR_PLL0_VCOPD_ASSERT);
+ tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
+ NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
+ NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP);
+
+ /* step 2 */
+ tegra_dc_sor_io_set_dpd(sor, 1);
+ udelay(15);
+
+ /* step 3 */
+ tegra_sor_write_field(sor, NV_SOR_PLL2,
+ NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
+ NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
+ udelay(25);
+
+ /* step 4 */
+ tegra_sor_write_field(sor, NV_SOR_PLL0,
+ NV_SOR_PLL0_PWR_MASK | /* PDPLL */
+ NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
+ NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
+ tegra_sor_write_field(sor, NV_SOR_PLL2,
+ NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
+ NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
+ udelay(225);
+
+ /* step 5 */
+ tegra_sor_write_field(sor, NV_SOR_PLL2,
+ NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */
+ NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
+
+ sor->power_is_up = 1;
+}
+
+#if DEBUG_SOR
+static void dump_sor_reg(struct tegra_dc_sor_data *sor)
+{
+#define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \
+ #a, a, tegra_sor_readl(sor, a));
+
+ DUMP_REG(NV_SOR_SUPER_STATE0);
+ DUMP_REG(NV_SOR_SUPER_STATE1);
+ DUMP_REG(NV_SOR_STATE0);
+ DUMP_REG(NV_SOR_STATE1);
+ DUMP_REG(NV_HEAD_STATE0(0));
+ DUMP_REG(NV_HEAD_STATE0(1));
+ DUMP_REG(NV_HEAD_STATE1(0));
+ DUMP_REG(NV_HEAD_STATE1(1));
+ DUMP_REG(NV_HEAD_STATE2(0));
+ DUMP_REG(NV_HEAD_STATE2(1));
+ DUMP_REG(NV_HEAD_STATE3(0));
+ DUMP_REG(NV_HEAD_STATE3(1));
+ DUMP_REG(NV_HEAD_STATE4(0));
+ DUMP_REG(NV_HEAD_STATE4(1));
+ DUMP_REG(NV_HEAD_STATE5(0));
+ DUMP_REG(NV_HEAD_STATE5(1));
+ DUMP_REG(NV_SOR_CRC_CNTRL);
+ DUMP_REG(NV_SOR_CLK_CNTRL);
+ DUMP_REG(NV_SOR_CAP);
+ DUMP_REG(NV_SOR_PWR);
+ DUMP_REG(NV_SOR_TEST);
+ DUMP_REG(NV_SOR_PLL0);
+ DUMP_REG(NV_SOR_PLL1);
+ DUMP_REG(NV_SOR_PLL2);
+ DUMP_REG(NV_SOR_PLL3);
+ DUMP_REG(NV_SOR_CSTM);
+ DUMP_REG(NV_SOR_LVDS);
+ DUMP_REG(NV_SOR_CRCA);
+ DUMP_REG(NV_SOR_CRCB);
+ DUMP_REG(NV_SOR_SEQ_CTL);
+ DUMP_REG(NV_SOR_LANE_SEQ_CTL);
+ DUMP_REG(NV_SOR_SEQ_INST(0));
+ DUMP_REG(NV_SOR_SEQ_INST(1));
+ DUMP_REG(NV_SOR_SEQ_INST(2));
+ DUMP_REG(NV_SOR_SEQ_INST(3));
+ DUMP_REG(NV_SOR_SEQ_INST(4));
+ DUMP_REG(NV_SOR_SEQ_INST(5));
+ DUMP_REG(NV_SOR_SEQ_INST(6));
+ DUMP_REG(NV_SOR_SEQ_INST(7));
+ DUMP_REG(NV_SOR_SEQ_INST(8));
+ DUMP_REG(NV_SOR_PWM_DIV);
+ DUMP_REG(NV_SOR_PWM_CTL);
+ DUMP_REG(NV_SOR_MSCHECK);
+ DUMP_REG(NV_SOR_XBAR_CTRL);
+ DUMP_REG(NV_SOR_DP_LINKCTL(0));
+ DUMP_REG(NV_SOR_DP_LINKCTL(1));
+ DUMP_REG(NV_SOR_DC(0));
+ DUMP_REG(NV_SOR_DC(1));
+ DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0));
+ DUMP_REG(NV_SOR_PR(0));
+ DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
+ DUMP_REG(NV_SOR_POSTCURSOR(0));
+ DUMP_REG(NV_SOR_DP_CONFIG(0));
+ DUMP_REG(NV_SOR_DP_CONFIG(1));
+ DUMP_REG(NV_SOR_DP_MN(0));
+ DUMP_REG(NV_SOR_DP_MN(1));
+ DUMP_REG(NV_SOR_DP_PADCTL(0));
+ DUMP_REG(NV_SOR_DP_PADCTL(1));
+ DUMP_REG(NV_SOR_DP_DEBUG(0));
+ DUMP_REG(NV_SOR_DP_DEBUG(1));
+ DUMP_REG(NV_SOR_DP_SPARE(0));
+ DUMP_REG(NV_SOR_DP_SPARE(1));
+ DUMP_REG(NV_SOR_DP_TPG);
+
+ return;
+}
+#endif
+
+static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
+ int is_lvds)
+{
+ const struct tegra_dc *dc = sor->dc;
+ const struct tegra_dc_dp_data *dp = dc->out;
+ const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg;
+ const struct soc_nvidia_tegra132_config *config = dc->config;
+
+ const int head_num = 0;
+ u32 reg_val = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num;
+ u32 vsync_end, hsync_end;
+ u32 vblank_end, hblank_end;
+ u32 vblank_start, hblank_start;
+
+ reg_val |= is_lvds ? NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
+ NV_SOR_STATE1_ASY_PROTOCOL_DP_A;
+ reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE |
+ NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER;
+
+ reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
+ reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
+ reg_val |= (link_cfg->bits_per_pixel > 18) ?
+ NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 :
+ NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444;
+
+ tegra_sor_writel(sor, NV_SOR_STATE1, reg_val);
+
+ /* Skipping programming NV_HEAD_STATE0, assuming:
+ interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */
+
+ tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
+ vtotal(config) << NV_HEAD_STATE1_VTOTAL_SHIFT |
+ htotal(config) << NV_HEAD_STATE1_HTOTAL_SHIFT);
+
+ vsync_end = config->vsync_width - 1;
+ hsync_end = config->hsync_width - 1;
+ tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
+ vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
+ hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
+
+ vblank_end = vsync_end + config->vback_porch;
+ hblank_end = hsync_end + config->hback_porch;
+ tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
+ vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
+ hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
+
+ vblank_start = vblank_end + config->yres;
+ hblank_start = hblank_end + config->xres;
+ tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
+ vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
+ hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
+
+ /* TODO: adding interlace mode support */
+ tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
+
+ tegra_sor_write_field(sor, NV_SOR_CSTM,
+ NV_SOR_CSTM_ROTCLK_DEFAULT_MASK |
+ NV_SOR_CSTM_LVDS_EN_ENABLE,
+ 2 << NV_SOR_CSTM_ROTCLK_SHIFT |
+ is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE :
+ NV_SOR_CSTM_LVDS_EN_DISABLE);
+
+ tegra_dc_sor_config_pwm(sor, 1024, 1024);
+}
+
+static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
+{
+ struct tegra_dc *dc = sor->dc;
+ struct display_controller *disp_ctrl = (void *)dc->base;
+
+ u32 reg_val = READL(&disp_ctrl->cmd.state_access);
+
+ WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
+ WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
+
+ /* Enable DC now - otherwise pure text console may not show. */
+ WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
+ WRITEL(reg_val, &disp_ctrl->cmd.state_access);
+}
+
+void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor)
+{
+ const struct tegra_dc_dp_link_config *link_cfg = sor->link_cfg;
+
+ tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL,
+ NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK,
+ NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
+
+ tegra_sor_write_field(sor, NV_SOR_PLL2,
+ NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
+ NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
+ udelay(25);
+
+ tegra_sor_write_field(sor, NV_SOR_PLL3,
+ NV_SOR_PLL3_PLLVDD_MODE_MASK,
+ NV_SOR_PLL3_PLLVDD_MODE_V3_3);
+ tegra_sor_writel(sor, NV_SOR_PLL0,
+ 0xf << NV_SOR_PLL0_ICHPMP_SHFIT |
+ 0x3 << NV_SOR_PLL0_VCOCAP_SHIFT |
+ NV_SOR_PLL0_PLLREG_LEVEL_V45 |
+ NV_SOR_PLL0_RESISTORSEL_EXT |
+ NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
+ tegra_sor_write_field(sor, NV_SOR_PLL2,
+ NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
+ NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
+ NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
+ NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE |
+ NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
+ tegra_sor_writel(sor, NV_SOR_PLL1,
+ NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE);
+
+ if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2,
+ NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
+ NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
+ 100, TEGRA_SOR_TIMEOUT_MS * 1000)) {
+ printk(BIOS_ERR, "DP failed to lock PLL\n");
+ return;
+ }
+
+ tegra_sor_write_field(sor, NV_SOR_PLL2,
+ NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK,
+ NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN |
+ NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
+
+ tegra_dc_sor_power_up(sor, 0);
+
+ /* re-enable SOR clock */
+ tegra_sor_enable_edp_clock(sor); /* select pll_dp as clock source */
+
+ /* Power up lanes */
+ tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
+
+ tegra_dc_sor_set_dp_mode(sor, link_cfg);
+
+}
+
+void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
+{
+ u32 reg_val;
+ struct display_controller *disp_ctrl = (void *)sor->dc->base;
+
+ tegra_dc_sor_enable_dc(sor);
+ tegra_dc_sor_config_panel(sor, 0);
+
+ WRITEL(0x9f00, &disp_ctrl->cmd.state_ctrl);
+ WRITEL(0x9f, &disp_ctrl->cmd.state_ctrl);
+
+ WRITEL(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE |
+ PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
+ &disp_ctrl->cmd.disp_pow_ctrl);
+
+ reg_val = tegra_sor_readl(sor, NV_SOR_TEST);
+ if (reg_val & NV_SOR_TEST_ATTACHED_TRUE)
+ return;
+
+ tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+ NV_SOR_SUPER_STATE1_ATTACHED_NO);
+
+ /*
+ * Enable display2sor clock at least 2 cycles before DC start,
+ * to clear sor internal valid signal.
+ */
+
+ /* Stop dc for 3 cycles */
+ WRITEL(0, &disp_ctrl->disp.disp_win_opt);
+ WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
+ udelay(FRAME_IN_MS * 1000 * 3);
+
+ /* Attach head */
+ tegra_dc_sor_update(sor);
+ tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+ NV_SOR_SUPER_STATE1_ATTACHED_YES);
+ tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+ NV_SOR_SUPER_STATE1_ATTACHED_YES |
+ NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
+ NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL);
+ tegra_dc_sor_super_update(sor);
+
+ /* wait for another 5 cycles */
+ udelay(FRAME_IN_MS * 1000 * 5);
+
+ /* Re-enable dc */
+ WRITEL(READ_MUX_ACTIVE | WRITE_MUX_ACTIVE,
+ &disp_ctrl->cmd.state_access);
+ WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
+
+ WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
+ WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
+
+ if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
+ NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
+ NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE,
+ 100, TEGRA_SOR_ATTACH_TIMEOUT_MS * 1000))
+ printk(BIOS_ERR, "dc timeout waiting for OPMOD = AWAKE\n");
+ else
+ printk(BIOS_INFO, "%s: sor is attached\n", __func__);
+
+#if DEBUG_SOR
+ dump_sor_reg(sor);
+#endif
+}
+
+void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
+ const struct tegra_dc_dp_link_config *link_cfg)
+{
+ tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
+ link_cfg->drive_current);
+ tegra_sor_writel(sor, NV_SOR_PR(sor->portnum),
+ link_cfg->preemphasis);
+ tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum),
+ link_cfg->postcursor);
+ tegra_sor_writel(sor, NV_SOR_LVDS, 0);
+
+ tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
+ tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
+
+ tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
+ NV_SOR_DP_PADCTL_TX_PU_ENABLE |
+ NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
+ NV_SOR_DP_PADCTL_TX_PU_ENABLE |
+ 2 << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT);
+
+ /* Precharge */
+ tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
+ 0xf0, 0xf0);
+ udelay(20);
+
+ tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
+ 0xf0, 0x0);
+}
+
+void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor)
+{
+ u32 drive_current = 0;
+ u32 pre_emphasis = 0;
+
+ /* Set to a known-good pre-calibrated setting */
+ switch (sor->link_cfg->link_bw) {
+ case SOR_LINK_SPEED_G1_62:
+ case SOR_LINK_SPEED_G2_7:
+ drive_current = 0x13131313;
+ pre_emphasis = 0;
+ break;
+ case SOR_LINK_SPEED_G5_4:
+ printk(BIOS_WARNING, "T124/T132 does not support 5.4G link"
+ " clock.\n");
+ default:
+ printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n",
+ sor->link_cfg->link_bw);
+ return;
+ }
+
+ tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
+ drive_current);
+ tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis);
+}
+
+void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor)
+{
+ u32 pad_ctrl = 0;
+ int err = 0;
+
+ switch (sor->link_cfg->lane_count) {
+ case 4:
+ pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
+ NV_SOR_DP_PADCTL_PD_TXD_1_NO |
+ NV_SOR_DP_PADCTL_PD_TXD_2_NO |
+ NV_SOR_DP_PADCTL_PD_TXD_3_NO);
+ break;
+ case 2:
+ pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
+ NV_SOR_DP_PADCTL_PD_TXD_1_NO |
+ NV_SOR_DP_PADCTL_PD_TXD_2_YES |
+ NV_SOR_DP_PADCTL_PD_TXD_3_YES);
+ break;
+ case 1:
+ pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
+ NV_SOR_DP_PADCTL_PD_TXD_1_YES |
+ NV_SOR_DP_PADCTL_PD_TXD_2_YES |
+ NV_SOR_DP_PADCTL_PD_TXD_3_YES);
+ break;
+ default:
+ printk(BIOS_ERR, "Invalid sor lane count: %u\n",
+ sor->link_cfg->lane_count);
+ return;
+ }
+
+ pad_ctrl |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN;
+ tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), pad_ctrl);
+
+ err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
+ if (err) {
+ printk(BIOS_ERR,
+ "Wait for lane power down failed: %d\n", err);
+ return;
+ }
+}
+
+void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor)
+{
+ const struct tegra_dc_dp_link_config *cfg = sor->link_cfg;
+ u32 val = 0;
+
+ switch (cfg->lane_count) {
+ case 4:
+ val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
+ NV_SOR_DP_PADCTL_PD_TXD_2_NO);
+ /* fall through */
+ case 2:
+ val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
+ /* fall through */
+ case 1:
+ val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
+ break;
+ default:
+ printk(BIOS_ERR,
+ "dp: invalid lane number %d\n", cfg->lane_count);
+ return;
+ }
+
+ tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
+ (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
+ (val << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
+ udelay(100);
+ tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
+ (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 0);
+}
+
+static u32 tegra_dc_poll_register(void *reg,
+ u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
+{
+ u32 temp = timeout_us;
+ u32 reg_val = 0;
+
+ do {
+ udelay(poll_interval_us);
+ reg_val = READL(reg);
+ if (timeout_us > poll_interval_us)
+ timeout_us -= poll_interval_us;
+ else
+ break;
+ } while ((reg_val & mask) != exp_val);
+
+ if ((reg_val & mask) == exp_val)
+ return 0; /* success */
+
+ return temp;
+}
+
+static void tegra_dc_sor_general_act(struct display_controller *disp_ctrl)
+{
+ WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
+
+ if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
+ GENERAL_ACT_REQ, 0, 100,
+ TEGRA_DC_POLL_TIMEOUT_MS*1000))
+ printk(BIOS_ERR,
+ "dc timeout waiting for DC to stop\n");
+}
+
+static struct tegra_dc_mode min_mode = {
+ .h_ref_to_sync = 0,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 1,
+ .v_sync_width = 1,
+ .h_back_porch = 20,
+ .v_back_porch = 0,
+ .h_active = 16,
+ .v_active = 16,
+ .h_front_porch = 1,
+ .v_front_porch = 2,
+};
+
+/* Disable windows and set minimum raster timings */
+static void
+tegra_dc_sor_disable_win_short_raster(struct display_controller *disp_ctrl,
+ int *dc_reg_ctx)
+{
+ int selected_windows, i;
+
+ selected_windows = READL(&disp_ctrl->cmd.disp_win_header);
+
+ /* Store and clear window options */
+ for (i = 0; i < DC_N_WINDOWS; ++i) {
+ WRITEL(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
+ dc_reg_ctx[i] = READL(&disp_ctrl->win.win_opt);
+ WRITEL(0, &disp_ctrl->win.win_opt);
+ WRITEL(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
+ }
+
+ WRITEL(selected_windows, &disp_ctrl->cmd.disp_win_header);
+
+ /* Store current raster timings and set minimum timings */
+ dc_reg_ctx[i++] = READL(&disp_ctrl->disp.ref_to_sync);
+ WRITEL(min_mode.h_ref_to_sync | (min_mode.v_ref_to_sync << 16),
+ &disp_ctrl->disp.ref_to_sync);
+
+ dc_reg_ctx[i++] = READL(&disp_ctrl->disp.sync_width);
+ WRITEL(min_mode.h_sync_width | (min_mode.v_sync_width << 16),
+ &disp_ctrl->disp.sync_width);
+
+ dc_reg_ctx[i++] = READL(&disp_ctrl->disp.back_porch);
+ WRITEL(min_mode.h_back_porch |
+ min_mode.v_back_porch << 16,
+ &disp_ctrl->disp.back_porch);
+
+ dc_reg_ctx[i++] = READL(&disp_ctrl->disp.front_porch);
+ WRITEL(min_mode.h_front_porch |
+ min_mode.v_front_porch << 16,
+ &disp_ctrl->disp.front_porch);
+
+ dc_reg_ctx[i++] = READL(&disp_ctrl->disp.disp_active);
+ WRITEL(min_mode.h_active | (min_mode.v_active << 16),
+ &disp_ctrl->disp.disp_active);
+
+ WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
+}
+
+/* Restore previous windows status and raster timings */
+static void
+tegra_dc_sor_restore_win_and_raster(struct display_controller *disp_ctrl,
+ int *dc_reg_ctx)
+{
+ int selected_windows, i;
+
+ selected_windows = READL(&disp_ctrl->cmd.disp_win_header);
+
+ for (i = 0; i < DC_N_WINDOWS; ++i) {
+ WRITEL(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
+ WRITEL(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
+ WRITEL(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
+ }
+
+ WRITEL(selected_windows, &disp_ctrl->cmd.disp_win_header);
+
+ WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
+ WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
+ WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
+ WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
+ WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
+
+ WRITEL(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
+}
+
+static void tegra_dc_sor_enable_sor(struct tegra_dc_sor_data *sor, int enable)
+{
+ struct display_controller *disp_ctrl = (void *)sor->dc->base;
+ u32 reg_val = READL(&disp_ctrl->disp.disp_win_opt);
+
+ reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE;
+ WRITEL(reg_val, &disp_ctrl->disp.disp_win_opt);
+}
+
+void tegra_dc_detach(struct tegra_dc_sor_data *sor)
+{
+ struct display_controller *disp_ctrl = (void *)sor->dc->base;
+ int dc_reg_ctx[DC_N_WINDOWS + 5];
+ unsigned long dc_int_mask;
+
+ /* Sleep mode */
+ tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+ NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
+ NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
+ NV_SOR_SUPER_STATE1_ATTACHED_YES);
+ tegra_dc_sor_super_update(sor);
+
+ tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx);
+
+ if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
+ NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
+ NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP,
+ 100, TEGRA_SOR_ATTACH_TIMEOUT_MS*1000)) {
+ printk(BIOS_ERR,
+ "dc timeout waiting for OPMOD = SLEEP\n");
+ }
+
+ tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
+ NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP |
+ NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE |
+ NV_SOR_SUPER_STATE1_ATTACHED_NO);
+
+ /* Mask DC interrupts during the 2 dummy frames required for detach */
+ dc_int_mask = READL(&disp_ctrl->cmd.int_mask);
+ WRITEL(0, &disp_ctrl->cmd.int_mask);
+
+ /* Stop DC->SOR path */
+ tegra_dc_sor_enable_sor(sor, 0);
+ tegra_dc_sor_general_act(disp_ctrl);
+
+ /* Stop DC */
+ WRITEL(DISP_CTRL_MODE_STOP, &disp_ctrl->cmd.disp_cmd);
+ tegra_dc_sor_general_act(disp_ctrl);
+
+ tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx);
+
+ WRITEL(dc_int_mask, &disp_ctrl->cmd.int_mask);
+}
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