[coreboot-gerrit] New patch to review for coreboot: c45fb4f rk3288: Fix memlayout to allow a little more bootblock space

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9609

-gerrit

commit c45fb4f7a387a07cbae907665c770f0d6a770918
Author: Julius Werner <jwerner at chromium.org>
Date:   Mon Dec 15 13:09:01 2014 -0800

    rk3288: Fix memlayout to allow a little more bootblock space
    
    Freeing up memory on rk3288 is like squeezing water out of a stone right
    now, but I still managed to get a few drops here and there. Let's hope
    this will be enough.
    
    BRANCH=None
    BUG=None
    TEST=Pinky builds and boots again. memsz is ~15K in bootblock and ~39K
    in verstage.
    
    Change-Id: Icf7ff3369bf367426a34f1490e0a041ae9bd6367
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 9a3737ab535cdef228a1607433860f881db04412
    Original-Change-Id: I90d9eab5b5d3af7a2e4b836a9c7b735b7c1c48e6
    Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/235870
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/soc/rockchip/rk3288/include/soc/memlayout.ld | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index e5c44a0..bb5af41 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -34,13 +34,13 @@ SECTIONS
 
 	SRAM_START(0xFF700000)
 	TTB(0xFF700000, 16K)
-	BOOTBLOCK(0xFF704004, 15K - 4)
-	TTB_SUBTABLES(0xFF707C00, 1K)
-	PRERAM_CBMEM_CONSOLE(0xFF708000, 4K)
-	VBOOT2_WORK(0xFF709000, 12K)
-	OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K)
-	PRERAM_CBFS_CACHE(0xFF716000, 4K)
-	STACK(0xFF717000, 4K)
+	BOOTBLOCK(0xFF704004, 17K - 4)
+	TTB_SUBTABLES(0xFF708400, 1K)
+	PRERAM_CBMEM_CONSOLE(0xFF708800, 4K)
+	VBOOT2_WORK(0xFF709800, 12K)
+	OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K)
+	PRERAM_CBFS_CACHE(0xFF717000, 1K)
+	STACK(0xFF717580, 3K - 0x180)
 	SRAM_END(0xFF718000)
 
 	/* 4K of special SRAM in PMU power domain.