[coreboot-gerrit] Patch merged into coreboot/master: 1109399 mips: disable caches in bootblock startup code

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 11093995e4cddfc6db16ad654c3e0d39440f74ff
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Sat Nov 29 14:35:49 2014 -0800

    mips: disable caches in bootblock startup code
    
    Until proper MIPS cache management is available it is necessary to
    disable data and instruction caches, otherwise code placed in memory
    stays in data cache and is not available for instruction fetched.
    
    BRANCH=none
    BUG=chrome-os-partner:31438,chrome-os-partner:34127
    TEST=coreboot loading rombase and rambase now succeeds.
    
    Change-Id: I4147e1325edc0b9bb951cd7ce18d5f104f3eaec0
    Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
    Original-Commit-Id: 93d5bfa1d01fbbabbabef33a22287ceeea28b15b
    Original-Change-Id: Ib195ed6e5f08ccaa6bbe3325c2199171bfb63b88
    Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/232191
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/9569
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/9569 for details.

-gerrit